Poly-phase frequency synthesis oscillator

• US 20090066427A1
• Filed: 02/19/2008
• Published: 03/12/2009
• Est. Priority Date: 02/04/2005
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Brennan, Aaron
• Granted Patent: US 8,085,100 B2
• Time in Patent Office: Days
• US Class Current: 331/45
• CPC Class Codes: G06F 7/68 using pulse rate multipliers or dividers pulse rate multipliers or dividers per seG06F7/70 takes precedence ; frequency division in electronic watches G04G3/02; frequency multiplication or division in oscillators H03B19/00; frequency dividing counters per se H03K23/00 - H03K29/00
• CPC Class Codes: H03H 2007/0192 Complex filters
• CPC Class Codes: H03H 7/21 providing two or more phase shifted output signals, e.g. n-phase output
• CPC Class Codes: H03K 5/00006 Changing the frequency modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle

Abstract

A frequency synthesis/multiplication circuit and method for multiplying the frequency of a reference signal. In one embodiment, multiple versions of the reference signal are generated having different phases relative to one another, and these multiple versions are combined to form an output signal having a frequency that is a multiple of the frequency of the reference signal.

Claims

1. A circuit, comprising:

a reference clock providing a reference clock signal operating at a reference frequency; and

a poly-phase frequency multiplier coupled with the reference clock signal, the poly-phase frequency multiplier providing an output signal with a frequency that is a multiple of the reference frequency, the poly-phase frequency multiplier having an input bias stage, a poly-phase filter stage, and a logic stage.

2. The circuit of claim 1, wherein the reference clock signal is a sinusoidal signal.

3. The circuit of claim 1, wherein the reference clock signal is a differential signal.

4. The circuit of claim 1, wherein the input bias stage includes at least one coupling capacitor for receiving the reference clock signal.

5. The circuit of claim 1, wherein the input bias stage has at least one resistor divider for offsetting the reference clock signal to a DC offset level.

6. The circuit of claim 1, wherein the poly-phase filter stage includes a first stage for generating at least two signals from the reference clock signal, the at least two signals including a first signal that is derived from the reference clock signal, and a second signal that is derived from reference clock signal and is shifted in phase by a first amount relative to the first signal.

7. The circuit of claim 6, wherein the at least two signals includes a third signal that is derived from the reference clock signal and is shifted in phase by a second amount, and a fourth signal that is derived from the reference clock signal and is shifted in phase by a third amount.

8. The circuit of claim 1, wherein the poly-phase filter stage includes a second stage for further filtering the at least two signals of the first poly-phase filter stage.

9. The circuit of claim 1, wherein the logic stage includes one or more exclusive-OR gates.

10. The circuit of claim 1, further comprising:

a frequency divider receiving the output signal of the poly-phase frequency multiplier and providing a divided signal output having a frequency that is a fraction of the frequency of the output signal.

19. The circuit of claim 1, further comprising:

a frequency divider receiving the output signal of the poly-phase frequency multiplier and providing a divided signal output having a frequency that is a fraction of the frequency of the output signal.

11. A circuit for multiplying a frequency of a reference signal, comprising:

an input bias stage coupled with the reference signal and generating a biased reference signal;

a filter stage receiving the biased reference signal, the filter stage generating a plurality of delayed signals derived from the reference signal;

and a logic stage receiving the plurality of delayed signals and generating an output signal having a frequency that is a multiple of the frequency of the reference signal.

12. The circuit of claim 11, wherein the reference signal is a differential sinusoidal signal.

13. The circuit of claim 11, wherein the input bias stage includes at least one coupling capacitor for receiving the reference signal.

14. The circuit of claim 11, wherein the input bias stage has at least one resistor divider for offsetting the reference signal to a DC offset level.

15. The circuit of claim 11, wherein the filter stage includes a first filter stage for generating at least two signals from the reference signal, the at least two signals including a first signal that is derived from the reference signal, and a second signal that is derived from reference signal and is shifted in phase by a first amount relative to the first signal.

16. The circuit of claim 15, wherein the at least two signals includes a third signal that is derived from the reference signal and is shifted in phase by a second amount, and a fourth signal that is derived from the reference signal and is shifted in phase by a third amount.

17. The circuit of claim 15, wherein the filter stage includes a second filter stage for further filtering the at least two signals of the first filter stage.

18. The circuit of claim 11, wherein the logic stage includes one or more exclusive-OR gates.

20. A method for multiplying a frequency of a reference signal, comprising:

generating multiple versions of the reference signal, each of said multiple versions having a different phase than the other of said multiple versions; and

combining said multiple versions of the signal to form an output signal having a frequency that is a multiple of the frequency of the reference signal.