Three dimensional structure memory
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Accused Products
Abstract
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
191 Citations
181 Claims
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1-87. -87. (canceled)
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88. A stacked integrated circuit memory comprising:
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at least one logic integrated circuit, wherein the at least one logic layer is at least one of a thinned flexible integrated circuit and capable of forming a thinned flexible integrated circuit; at least one thinned substantially flexible memory integrated circuit positioned in a stacked relation to one another; and interconnections electrically connecting the at least one logic integrated circuit and the at least one thinned substantially flexible memory integrated circuit. - View Dependent Claims (89, 90, 91, 92, 93, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106)
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107. A stacked integrated circuit memory comprising:
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a logic layer, wherein the logic layer is at least one of a thinned flexible integrated circuit and capable of forming a thinned flexible integrated circuit; at least one thin substantially flexible memory layer formed overlying the logic layer; and a plurality of connections internal to the stacked integrated circuit for transferring a plurality of data bytes between the logic layer and the at least one thin substantially flexible memory layer. - View Dependent Claims (108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124)
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125. An integrated circuit comprising:
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a data source in one integrated circuit layer formed with a low stress dielectric, wherein the integrated circuit layer is at least one of a thinned flexible integrated circuit and capable of forming a thinned flexible integrated circuit; a data sink in a circuit layer formed overlying the data source integrated circuit layer, there being a volume within which the integrated circuit and circuit layer overlie one another; and interconnect circuitry within said volume for transferring control signals and a plurality of data bytes between the data source and data sink. - View Dependent Claims (94, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143)
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144. An integrated circuit comprising:
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a data source in one integrated circuit layer formed with a low stress dielectric, wherein the integrated circuit layer is at least one of a thinned flexible integrated circuit and capable of forming a thinned flexible integrated circuit; a data sink in a circuit layer overlying the data source integrated circuit layer, there being a volume within which the integrated circuit and circuit layer overlie one another; and interconnect circuitry within said volume for transferring control signals and a plurality of data bytes between the data source and data sink. - View Dependent Claims (145, 146, 147, 148, 149, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162)
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150. The device of claim 187, wherein the different process technology is one of DRAM, SRAM, FLASH, EEPROM, EPROM, Ferroelectric and Giant Magneto Resistance.
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163. An integrated circuit comprising:
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a data source in a first circuit layer formed with a low stress dielectric, wherein the first circuit layer is at least one of a thinned flexible integrated circuit and capable of forming a thinned flexible integrated circuit; a data sink in a second circuit layer; the first and second circuit layers substantially overlie each other; and interconnect circuitry between the data source and data sink interconnecting the data source and data sink for transferring control signals between the data source and the data sink and for transferring a plurality of data bytes between the data source and data sink. - View Dependent Claims (164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181)
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Specification