Sense amplifier circuitry for integrated circuit having memory cell array, and method of operating same

• US 20090067218A1
• Filed: 07/18/2008
• Published: 03/12/2009
• Est. Priority Date: 09/06/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Graber, Philippe
• Granted Patent: US 7,787,319 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/067 Single-ended amplifiers

Abstract

An integrated circuit device (e.g., a logic device or a memory device) having (i) a memory cell array which includes a plurality of memory cells (for example, memory cells having electrically floating body transistors) and (ii) sense amplifier circuitry, coupled to the memory cell array, to sense a data state stored in one of the memory cells during a sense phase of operation. In one embodiment, the sense amplifier circuitry includes first and second capacitors, a first input electrically coupled to (i) the memory cell to receive a signal which is representative of the data state stored therein and (ii) a first terminal of the first capacitor, and a second input electrically coupled to (i) a first predetermined voltage and (ii) a first terminal of the second capacitor. The sense amplifier circuitry further includes a current source and a transistor wherein the gate of the transistor is electrically coupled to the second terminals of the first and second capacitors, and a first region of the transistor is electrically coupled to the current source.

Claims

1. An integrated circuit device comprising:

a memory cell array having a plurality of memory cells;

sense amplifier circuitry, coupled to the memory cell array, to sense a data state stored in a memory cell wherein the memory cell is one of the plurality of the memory cells in the memory cell array, the sense amplifier circuitry including;

first and second capacitors, each capacitor having first and second terminals;

a first input electrically coupled to (i) the memory cell to receive a signal which is representative of the data state stored in the memory cell and (ii) the first terminal of the first capacitor;

a second input electrically coupled to (i) a first predetermined voltage and (ii) the first terminal of the second capacitor;

a first current source having first and second terminals;

a first transistor having a gate, a first region and a second region, wherein;

the gate is electrically coupled to the second terminals of the first and second capacitors, and

the first region is electrically coupled to the first terminal of the first current source; and

wherein, during a sense phase of operation of the sense amplifier circuitry, the sense amplifier circuitry senses the data state stored in the memory cell based on the signal which is representative of the data state stored in the memory cell.

2. The integrated circuit device of claim 1 wherein the transistor is a p-channel type transistor or n-channel type transistor.

3. The integrated circuit device of claim 1 wherein a trip voltage of the sense amplifier circuitry is correlated to a ratio of the capacitances of the first and second capacitors.

4. The integrated circuit device of claim 1 wherein the sense amplifier circuitry further includes:

first selection circuit, disposed between the first input and the memory cell array, to electrically couple the memory cell to the first input during the sense phase of operation of the sense amplifier circuitry; and

second selection circuit, disposed between the second input and the first predetermined voltage, to responsively couple the first predetermined voltage to the second input during the sense phase of operation.

5. The integrated circuit device of claim 4 wherein the second selection circuit, during a precharge phase of operation of the sense amplifier circuitry, electrically couples a second predetermined voltage to the second input.

6. The integrated circuit device of claim 5 wherein a trip voltage of the sense amplifier circuitry is correlated to a ratio of the capacitances of the first and second capacitors multiplied by the amplitude of the second predetermined voltage.

7. The integrated circuit device of claim 5 wherein the first selection circuit, during the precharge phase of operation of the sense amplifier circuitry, electrically couples a third predetermined voltage to the first input.

8. The integrated circuit device of claim 1 wherein the sense amplifier circuitry further includes a feedback switch to electrically couple the gate of the first transistor to, or decouple the gate of the first transistor from the first region of the transistor wherein during the sense phase of operation, the feedback switch electrically decouples the gate of the first transistor from the first region of the first transistor.

9. The integrated circuit device of claim 8 wherein during a precharge phase of operation of the sense amplifier circuitry, the feedback switch electrically couples the gate of the first transistor from the first region of the first transistor.

10. The integrated circuit device of claim 1 wherein the sense amplifier circuitry further includes:

a second current source having first and second terminals;

a second transistor having a gate, a first region and a second region, wherein;

the gate of the second transistor is coupled to the first region of the first transistor, and

the first region of the second transistor is electrically coupled to the first terminal of the second current source; and

wherein, during a sense phase of operation of the sense amplifier circuitry, the sense amplifier circuitry outputs a signal which is representative of the data state stored in the memory cell using the signal which is representative of the data state stored in the memory cell.

11. The integrated circuit device of claim 1 wherein the sense amplifier circuitry further includes an enable transistor, coupled to the first and/or second inputs of the sense amplifier circuitry, to responsively enable the sense amplifier circuitry to, or disable the sense amplifier circuitry from sensing the data state stored in the memory cell.

12. The integrated circuit device of claim 1 wherein the enable transistor is capacitively coupled to the first and/or second inputs of the sense amplifier circuitry.

13. The integrated circuit device of claim 1 wherein the memory cell includes an electrically floating body transistor and wherein the data state of the memory cell is stored in a body region of the electrically floating body transistor.

14. The integrated circuit device of claim 13 wherein the memory cell includes an electrically floating body transistor and wherein the amplitude of the signal which is representative of the data state stored in the memory cell is responsive to the amount of current conducted by the electrically floating body transistor of the memory cell during the sense phase of operation of the sense amplifier circuitry.

15. The integrated circuit device of claim 1 wherein the sense amplifier circuitry further includes a bit line input coupler circuit, disposed between the first input and the memory cell array, to electrically and indirectly couple the memory cell to the first input during the sense phase of operation of the sense amplifier circuitry.

16. An integrated circuit device comprising:

a memory cell array having a plurality of memory cells;

sense amplifier circuitry, coupled to the memory cell array, to sense a data state stored in a memory cell wherein the memory cell is one of the plurality of the memory cells in the memory cell array, the sense amplifier circuitry including;

first, second and third capacitors, each capacitor including first and second terminals;

a first input electrically coupled to (i) the memory cell to receive a signal which is representative of the data state stored in the memory cell and (ii) the first terminal of the first capacitor;

a second input electrically coupled to (i) a first predetermined voltage and (ii) the first terminal of the second capacitor;

first and second current sources, each current source including first and second terminals;

first and second transistors, each transistor including a gate, a first region and a second region, wherein;

the gate of the first transistor is electrically coupled to the second terminals of the first and second capacitors,

the first region of the first transistor is electrically coupled to the first terminal of the first current source and the first terminal of the third capacitor,

the gate of the second transistor is electrically coupled to the second terminal of the third capacitor, and

the first region of the second transistor is electrically coupled to the first terminal of the second current source; and

wherein, during a sense phase of operation of the sense amplifier circuitry, the sense amplifier circuitry sense the data state stored in the memory cell based on the signal which is representative of the data state stored in the memory cell.

17. The integrated circuit device of claim 16 wherein the sense amplifier circuitry further includes an output, which is electrically coupled to the first region of the transistor and wherein, during a sense phase of operation of the sense amplifier circuitry, the sense amplifier circuitry outputs a signal which is representative of the data state of the memory cell using the signal which is representative of the data state stored in the memory cell.

18. The integrated circuit device of claim 16 wherein the first and second transistors are p-channel or n-channel type transistors.

19. The integrated circuit device of claim 16 wherein the sense amplifier circuitry further includes:

a first feedback switch to electrically couple the gate of the first transistor to, or decouple the gate of the first transistor from the first region of the first transistor;

a second feedback switch to electrically couple the gate of the second transistor to, or decouple the gate of the second transistor from the first region of the second transistor;

wherein during the sense phase of operation of the sense amplifier circuitry, the first and second feedback switches electrically decouple the gates of the first and second transistors, respectively, from the first regions of the first and second transistors, respectively.

20. The integrated circuit device of claim 19 wherein during a precharge phase of operation of the sense amplifier circuitry, the first and second feedback switches electrically couple the gates of the first and second transistors, respectively, from the first regions of the first and second transistors, respectively.

21. The integrated circuit device of claim 16 wherein a trip voltage of the sense amplifier circuitry is correlated to a ratio of the capacitances of the first and second capacitors.

22. The integrated circuit device of claim 16 wherein the sense amplifier circuitry further includes:

first selection circuit, disposed between the first input and the memory cell array, to electrically couple the memory cell to the first input during the sense phase of operation of the sense amplifier circuitry; and

second selection circuit, disposed between the second input and the first predetermined voltage, to couple the first predetermined voltage to the second input during the sense phase of operation.

23. The integrated circuit device of claim 22 wherein the second selection circuit, during a precharge phase of operation of the sense amplifier circuitry, electrically couples a second predetermined voltage to the second input.

24. The integrated circuit device of claim 23 wherein a trip voltage of the sense amplifier circuitry is correlated to a ratio of the capacitances of the first and second capacitors multiplied by the amplitude of the second predetermined voltage.

25. The integrated circuit device of claim 23 wherein the first selection circuit, during the precharge phase of operation of the sense amplifier circuitry, electrically couples a third predetermined voltage to the first input.

26. The integrated circuit device of claim 16 wherein the sense amplifier circuitry further includes:

a third current source having first and second terminals;

a third transistor having a gate, a first region and a second region, wherein;

the gate of the third transistor is coupled to the first region of the second transistor, and

the first region of the third transistor is electrically coupled to the first terminal of the third current source; and

wherein, during a sense phase of operation of the sense amplifier circuitry, the sense amplifier circuitry outputs a signal which is representative of the data state stored in the memory cell using the signal which is representative of the data state stored in the memory cell.

27. The integrated circuit device of claim 16 further including latch circuitry to latch the data state of the signal output by the sense amplifier circuitry, wherein the first region of the second transistor is electrically coupled to latch circuitry.

28. The integrated circuit device of claim 16 wherein the sense amplifier circuitry further includes an enable transistor, coupled to the first and/or second inputs of the sense amplifier circuitry, to responsively enable the sense amplifier circuitry to, or disable the sense amplifier circuitry from sensing the data state stored in the memory cell.

29. The integrated circuit device of claim 16 wherein the enable transistor is capacitively coupled to the first and/or second inputs of the sense amplifier circuitry.

30. The integrated circuit device of claim 16 wherein the memory cell includes an electrically floating body transistor and wherein the data state of the memory cell is stored in a body region of the electrically floating body transistor.

31. The integrated circuit device of claim 30 wherein the memory cell includes an electrically floating body transistor and wherein the amplitude of the signal which is representative of the data state stored in the memory cell is responsive to the amount of current conducted by the electrically floating body transistor of the memory cell during the sense phase of operation of the sense amplifier circuitry.

32. The integrated circuit device of claim 16 wherein the sense amplifier circuitry further includes a bit line input coupler circuit, disposed between the first input and the memory cell array, to electrically and indirectly couple the memory cell to the first input during the sense phase of operation of the sense amplifier circuitry.