SEMICONDUCTOR MEMORY DEVICE FOR WRITING DATA TO MULTIPLE CELLS SIMULTANEOUSLY AND REFRESH METHOD THEREOF

• US 20090067229A1
• Filed: 09/05/2008
• Published: 03/12/2009
• Est. Priority Date: 09/10/2007
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KANG, Hee Bok, HONG, Suk Kyoung
• Granted Patent: US 7,961,534 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 2013/0052 Read process characterized by the shape, e.g. form, length, amplitude of the read pulse
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse
• CPC Class Codes: G11C 2213/15 Current-voltage curve
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a source line, and the cells are configured to read and write data according to a cell driving voltage. Each switching element of a plurality of switching elements are connected in parallel with a single cell of the plurality of cells, and the plurality of switching elements are controlled selectively by a plurality of bit lines.

Claims

1. A semiconductor memory device comprising:

a read/write bit line configured to supply a cell driving voltage;

a selecting unit connected to the read/write bit line and controlled by a word line;

a plurality of cells connected between the selecting unit and a source line and configured to read/write data according to the cell driving voltage; and

a plurality of switching elements connected in parallel to the plurality of cells and controlled selectively by a plurality of bit lines.

2. The semiconductor memory device according to claim 1, wherein the selecting unit comprises a selecting switch configured to control a connection between the read/write bit line and the first cell of the plurality of cells according to the word line.

3. The semiconductor memory device according to claim 1, wherein each switching element of the plurality of switching elements comprises a MOS transistor.

4. The semiconductor memory device according to claim 1, wherein each switching element of the plurality of switching elements comprises a bipolar junction transistor.

5. The semiconductor memory device according to claim 1, wherein each switching element of the plurality of switching elements comprises a PNPN diode.

6. The semiconductor memory device according to claim 1, wherein each switching element the plurality of switching elements is connected in parallel to a single cell the plurality of cells.

7. The semiconductor memory device according to claim 1, further comprising:

a write driving unit configured to selectively supply a driving voltage to the plurality of bit lines;

a global write driving unit configured to supply the cell driving voltage to the read/write bit line; and

a source driving unit configured to supply a ground voltage or a write voltage to the source line.

8. The semiconductor memory device according to claim 1, wherein each cell of the plurality of cells comprises a phase change resistance cell, the phase change resistance cell comprising a phase change resistor.

9. The semiconductor memory device according to claim 1, wherein each cell of the plurality of cells comprises a Magnetic Tunnel Junction (MTJ) cell, the MTJ cell comprising an MTJ element.

10. The semiconductor memory device according to claim 1, wherein each cell of the plurality of cells comprises a resistance switch cell, the resistance switch cell comprising a resistive switch element.

11. The semiconductor memory device according to claim 1, wherein the read/write bit line is shared by a plurality of selecting units.

12. The semiconductor memory device according to claim 1, wherein the source line is shared by a plurality of cells connected to a bit line.

13. A semiconductor memory device comprising:

a cell array comprising a phase change resistance cell configured to read and write data;

a register configured to store information of the cell array; and

a refresh control means configured to perform a refresh operation with a specific refresh cycle using the information stored in the register, and to improve a retention characteristic of data stored in the cell array.

14. The semiconductor memory device according to claim 13, wherein the phase change resistance cell includes:

a phase change resistor configured to sense a change in crystallization state and to store data corresponding to a corresponding resistance change,

wherein the crystallization state is changed according to currents applied to the phase change resistor through a bit line; and

a switching element connected between the phase change resistor and a source line and controlled by a word line.

15. The semiconductor memory device according to claim 13, wherein the phase change resistance cell comprises:

a phase change resistor configured to sense a change in crystallization state and to store data corresponding to a corresponding resistance change,

wherein the crystallization state is changed according to currents applied to the phase change resistor through a bit line; and

a diode element connected between the phase change resistor and the word line.

16. The semiconductor memory device according to claim 13, wherein the refresh control means comprises:

a refresh control unit configured to control a refresh operation in response to a refresh control signal and to output a count address for the refresh operation;

a row address controller configured to output the signal and row address to the cell array by latching and decoding a row address inputted in response to a Row Address Strobe (RAS) signal and an output signal of the refresh control unit, and to output the count address to the cell array by selecting the count address in the refresh operation;

a column address controller configured to latch and decode a column address inputted in response to a Column Address Strobe (CAS) signal; and

an input/output logic unit configured to control read/write operations of the cell array in response to an output enable signal and read/write commands.

17. The semiconductor memory device according to claim 16, wherein the refresh control unit comprises:

a refresh register configured to store nonvolatile parameter information for controlling a refresh operation and to output the refresh control signal in the refresh operation;

a refresh controller configured to output a refresh signal and a refresh enable signal for performing a refresh operation in response to the refresh control signal; and

a refresh counter configured to count a refresh cycle in response to the refresh signal so as to output the count address.

18. The semiconductor memory device according to claim 13, wherein the cell array further comprises:

a sense amplifier configured to sense and amplify data stored in the cell array; and

a write driving unit configured to supply a driving voltage corresponding to write data to the cell array.

19. A semiconductor memory device comprising:

a cell array comprising a phase change resistance cell, the phase change resistance cell configured to read and write data; and

a refresh control means configured to perform a refresh operation with a specific refresh cycle according to information stored in the register so as to improve a retention characteristic of data stored in the cell array, wherein the cell array comprises

a read/write bit line configured to supply a cell driving voltage;

a selecting unit connected to the read/write bit line and controlled by a word line;

a plurality of phase change resistance cells connected between the selecting unit and a source line and configured to read/write data according to the cell driving voltage; and

a plurality of switching elements connected in parallel to the plurality of phase change resistance cells and controlled selectively by a plurality of bit lines.

20. The semiconductor memory device according to claim 19, wherein the cell array further comprises:

a sense amplifier configured to sense and amplify data stored in the cell array;

a write driving unit configured to selectively supply a driving voltage to the plurality of bit lines;

a global write driving unit configured to supply the cell driving voltage to the read/write bit line;

a source driving unit configured to supply a ground voltage or a write voltage to the source line; and

a register configured to store data of the sense amplifier.

21. The semiconductor memory device according to claim 19, wherein the refresh control means comprises:

a refresh control unit configured to control a refresh operation in response to a refresh control signal and to output a count address for the refresh operation;

a row address controller configured to output the signal and row address to the cell array by latching and decoding a row address inputted in response to a RAS signal and an output signal of the refresh control unit, and to output the count address to the cell array by selecting the count address in the refresh operation;

a column address controller configured to latch and decode a column address inputted in response to a CAS signal; and

an input/output logic unit configured to control read/write operations of the cell array in response to an output enable signal and read/write commands.

22. The semiconductor memory device according to claim 21, wherein the refresh control unit comprises:

a refresh register configured to store nonvolatile parameter information for controlling a refresh operation and to output the refresh control signal in the refresh operation;

a refresh controller configured to output a refresh signal and a refresh enable signal for performing a refresh operation in response to the refresh control signal; and

a refresh counter configured to count a refresh cycle in response to the refresh signal and output the count address.

23. A refresh method of a semiconductor memory device, the method comprising the steps of:

reading and writing data in a cell array, the cell array comprising a phase change resistor configured to store data corresponding to resistance change, wherein the resistance change corresponds to a change in crystallization state of the phase change resistor that depends on currents applied to the phase change resistor through a bit line; and

refreshing data of the cell array with a specific predetermined refresh cycle so as to improve retention characteristics of data stored in the cell array.

24. The refresh method according to claim 23, wherein the step of refreshing data of the cell array comprises the steps of:

reading refresh count information previously stored with a nonvolatile phase and power off time information;

sensing a power on state;

reading data stored in the cell array and storing the data in a register;

determining whether a refresh time is exceeded in a refresh operation; and

restoring the data stored in the register in the cell array.

25. The refresh method according to claim 24, wherein the step of determining whether the refresh time is exceeded further comprises uploading memory data to perform a refresh operation when the refresh time is exceeded, and performing the previous refresh operation when the refresh time is not exceeded.