NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
First Claim
1. A nonvolatile semiconductor memory device comprising:
- a semiconductor region;
first and second cell units formed in the semiconductor region;
a first bit line connected to one end of the first cell unit;
a second bit line connected to one end of the second cell unit;
a source line connected to the other ends of the first and second cell units; and
a control circuit which controls the semiconductor region, the first and second bit lines, and the source line,wherein the first cell unit is comprised of;
a first cell transistor having a charge storage layer and a control gate electrode;
a first select gate transistor connected between the first cell transistor and the first bit line; and
a second select gate transistor connected between the first cell transistor and the source line,wherein the second cell unit is comprised of;
a second cell transistor having a charge storage layer and a control gate electrode;
a third select gate transistor connected between the second cell transistor and the second bit line; and
a fourth select gate transistor connected between the second cell transistor and the source line, andwherein the control circuit is comprised of;
first means for making the first bit line floating, after pre-charging the first bit line to a first potential;
second means for varying the first bit line from the first potential to a third potential by providing a second potential to the second bit line, the semiconductor region and the source line with the first bit line in the floating state; and
third means for reading data of the first cell transistor to the first bit line, after setting the first bit line to the third potential.
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Accused Products
Abstract
A memory device includes a control circuit which controls a semiconductor region, a first bit line, a second bit line and a source line. The control circuit is comprised of means for making the first bit line floating, after pre-charging the first bit line to a first potential, means for varying the first bit line from the first potential to a third potential by providing a second potential to the second bit line, the semiconductor region and the source line with the first bit line in the floating state, and means for reading data of the first cell transistor to the first bit line, after setting the first bit line to the third potential.
24 Citations
22 Claims
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1. A nonvolatile semiconductor memory device comprising:
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a semiconductor region; first and second cell units formed in the semiconductor region; a first bit line connected to one end of the first cell unit; a second bit line connected to one end of the second cell unit; a source line connected to the other ends of the first and second cell units; and a control circuit which controls the semiconductor region, the first and second bit lines, and the source line, wherein the first cell unit is comprised of; a first cell transistor having a charge storage layer and a control gate electrode; a first select gate transistor connected between the first cell transistor and the first bit line; and a second select gate transistor connected between the first cell transistor and the source line, wherein the second cell unit is comprised of; a second cell transistor having a charge storage layer and a control gate electrode; a third select gate transistor connected between the second cell transistor and the second bit line; and a fourth select gate transistor connected between the second cell transistor and the source line, and wherein the control circuit is comprised of; first means for making the first bit line floating, after pre-charging the first bit line to a first potential; second means for varying the first bit line from the first potential to a third potential by providing a second potential to the second bit line, the semiconductor region and the source line with the first bit line in the floating state; and third means for reading data of the first cell transistor to the first bit line, after setting the first bit line to the third potential. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A nonvolatile semiconductor memory device comprising:
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a semiconductor region; first and second cell units formed in the semiconductor region; a first bit line connected to one end of the first cell unit; a second bit line connected to one end of the second cell unit; a source line connected to the other ends of the first and second cell units; and a control circuit which controls the semiconductor region, the first and second bit lines, and the source line, wherein the first cell unit is comprised of; a first cell transistor having a charge storage layer and a control gate electrode; a first select gate transistor connected between the first cell transistor and the first bit line; and a second select gate transistor connected between the first cell transistor and the source line, wherein the second cell unit is comprised of; a second cell transistor having a charge storage layer and a control gate electrode; a third select gate transistor connected between the second cell transistor and the second bit line; and a fourth select gate transistor connected between the second cell transistor and the source line, and wherein the control circuit is comprised of; first means for making the first bit line floating, after pre-charging the first bit line to a first potential; second means for varying the first bit line from the first potential to a third potential by providing a second potential to the second bit line with the first bit line in the floating state; and third means for reading data of the first cell transistor to the first bit line, after setting the first bit line to the third potential. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification