NONVOLATILE MEMORY AND METHOD FOR ON-CHIP PSEUDO-RANDOMIZATION OF DATA WITHIN A PAGE AND BETWEEN PAGES
First Claim
1. An integrated-circuit memory chip, comprising:
- an array of nonvolatile memory cells accessible page by page, each page being a group of memory cells, each memory cell of the group being in a column of the array and along a row accessible by a common word line;
a sequence of starting column positions so that each page to be programmed has an associated starting column position;
an address generator for generating an address for the associated starting column position;
a set of data latches associated with each column responsive to the address generator for staging data to be programmed into each page, the staged data starting from the associated starting column position and wrapping around until the page is filled; and
a programming circuit to program in parallel the staged data into each page.
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Accused Products
Abstract
Features within an integrated-circuit memory chip enables scrambling or randomization of data stored in an array of nonvolatile memory cells. In one embodiment, randomization within each page helps to control source loading errors during sensing and floating gate to floating gate coupling among neighboring cells. Randomization from page to page helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. In another embodiment, randomization is implemented both within a page and between pages. The scrambling or randomization may be predetermined, or code generated pseudo randomization or user driven randomization in different embodiments. These features are accomplished within the limited resource and budget of the integrated-circuit memory chip.
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Citations
23 Claims
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1. An integrated-circuit memory chip, comprising:
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an array of nonvolatile memory cells accessible page by page, each page being a group of memory cells, each memory cell of the group being in a column of the array and along a row accessible by a common word line; a sequence of starting column positions so that each page to be programmed has an associated starting column position; an address generator for generating an address for the associated starting column position; a set of data latches associated with each column responsive to the address generator for staging data to be programmed into each page, the staged data starting from the associated starting column position and wrapping around until the page is filled; and a programming circuit to program in parallel the staged data into each page. - View Dependent Claims (2, 3, 4, 5, 6, 7, 11)
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8. An integrated-circuit memory chip, comprising:
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an array of nonvolatile memory cells accessible page by page, each page being a group of memory cells, each memory cell of the group being in a column of the array and along a row accessible by a common word line; first and second encodings for each set of columns in which data is to be programmed; a sequence of polarity bits, one for a set of columns of a page; an encoder to encode the data bits associated with each set of columns with either first or second encoding according to whether the polarity bit for the set of columns is in a first or second state; and a programming circuit to program in parallel the encoded data into each page. - View Dependent Claims (9, 10)
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12. In an integrated-circuit memory chip having an array of nonvolatile memory cells accessible page by page, each page being a group of memory cells, each memory cell of the group being in a column of the array and along a row accessible by a common word line, a method for programming data into the array comprising:
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generating on-chip a sequence of starting column positions so that each page to be programmed has an associated starting column position; staging data to be programmed into each page by starting from the associated starting column position and wrapping around until the page is filled; and programming the staged data in parallel into each page. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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21. In an integrated-circuit memory chip having an array of nonvolatile memory cells accessible page by page, each page being a group of memory cells, each memory cell of the group being in a column of the array and along a row accessible by a common word line, a method for programming data into the array comprising:
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providing first and second encodings for each set of columns in which data is to be programmed; generating on-chip a sequence of polarity bits, one for each set of columns of a page; encoding the data bit associated with each set of columns with either first or second encoding according to whether the polarity bit for each set of columns is in a first or second state; and programming in parallel the encoded data into each page. - View Dependent Claims (22, 23)
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Specification