REDUCING NOISE IN SEMICONDUCTOR DEVICES
First Claim
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1. A method for reducing noise in a semiconductor device, comprising:
- applying a reset voltage to a control gate of the semiconductor device for a period of time; and
sensing a state of the semiconductor device after applying the reset voltage.
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Abstract
The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage.
27 Citations
25 Claims
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1. A method for reducing noise in a semiconductor device, comprising:
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applying a reset voltage to a control gate of the semiconductor device for a period of time; and sensing a state of the semiconductor device after applying the reset voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 22)
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10. A method for reducing noise in a semiconductor device, comprising:
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exposing the semiconductor device to a field such that the semiconductor device is in a state of accumulation to facilitate detrapping of dielectric interface traps; transitioning the semiconductor device from a state of accumulation to inversion in a period of time substantially less than a period of time associated with 1/f noise; and sensing a state of the semiconductor device. - View Dependent Claims (11, 12, 13, 14)
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15. A semiconductor device comprising:
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an array of memory cells arranged in rows and columns, wherein the cells arranged in at least one of the rows are coupled by a select line and wherein the cells arranged in at least one of the columns are coupled by a sense line; and control circuitry coupled to the array, wherein the control circuitry is operable to; apply a reset voltage to a control gate of at least one selected memory cell for a time prior to sensing a state of the at least one selected memory cell; and apply a sensing voltage ramp to the control gate of the at least one selected memory cell. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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23. A semiconductor device comprising:
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an array of memory cells arranged in rows and columns, wherein the cells arranged in at least one of the rows are coupled by a select line and wherein the cells arranged in at least one of the columns are coupled by a sense line; and control circuitry coupled to the array, wherein the control circuitry is operable to; apply a reset voltage to a control gate of at least one selected memory cell for a time prior to applying each of a number of discrete sensing voltages to the control gate to sense the state of the at least one selected memory cell; and apply a first discrete sensing voltage, which is less than a second discrete sensing voltage used to sense a higher state than the first discrete sensing voltage, and greater than a third discrete sensing voltage used to sense a lowermost state; apply the second discrete sensing voltage after the first discrete sensing voltage; and apply the third discrete sensing voltage after the first discrete sensing voltage. - View Dependent Claims (24, 25)
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Specification