Method for Non-Volatile Memory With Background Data Latch Caching During Read Operations

• US 20090067253A1
• Filed: 11/03/2008
• Published: 03/12/2009
• Est. Priority Date: 04/01/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Yan Li
• Inventors: Li, Yan
• Granted Patent: US 7,733,703 B2
• Time in Patent Office: Days
• US Class Current: 365/185.210
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A read caching scheme is implemented for memory cells where more than one bit is sensed together, such as sensing all of the n bits of each memory cell of a physical page together. The n-bit physical page of memory cells sensed correspond to n logical binary pages, one for each of the n-bits. Each of the binary logical pages is being output in each cycle, while the multi-bit sensing of the physical page is performed every nth cycles.

Claims

1. A method of reading a non-volatile memory having addressable pages of memory cells on associated wordlines, comprising:

sensing a group of n binary pages together and latching the n binary pages;

outputting each one of the n latched binary pages of data every operating cycle starting from a given cycle; and

wherein said sensing and latching are performed every nth operating cycles during one of said outputting of a latched binary page from a previous operating cycle.

2. The method as in claim 1, wherein n is the number of bits stored in an individual memory cell of the non-volatile memory.

3. The method as in claim 1, wherein n is 2.

4. The method as in claim 1, wherein n is greater than 2.

5. The method as in claim 1, wherein the non-volatile memory is flash memory.

6. A non-volatile memory device having addressable pages of memory cells on associated wordlines, comprising:

sensing circuits for sensing a group of n binary pages together and latching the n binary pages;

an input/output bus controlled for outputting one of the n latched binary pages of data every operating cycle starting from a given cycle; and

wherein said sensing circuits for sensing and latching are active every nth operating cycles while said input/output bus is outputting a latched binary page.

7. The non-volatile memory as in claim 6, wherein n is the number of bits stored in an individual memory cell of the non-volatile memory.

8. The non-volatile memory as in claim 6, wherein n is 2.

9. The non-volatile memory as in claim 6, wherein n is greater than 2.

10. The non-volatile memory as in claim 6, wherein the non-volatile memory is flash memory.