Thin gate stack structure for non-volatile memory cells and methods for forming the same

• US 20090067256A1
• Filed: 09/06/2007
• Published: 03/12/2009
• Est. Priority Date: 09/06/2007
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Derderian, Garo, Bhattacharyya, Arup
• Application Number:
  US11/899,644
• Publication Number:
  US 20090067256A1
• Time in Patent Office: Days
• US Class Current: 365/185.280
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate

Abstract

Embodiments are described for reducing the programming voltage of a memory cell in a memory device. The memory cell includes a channel region extending between first and second diffusion regions formed in a substrate. A tunnel dielectric material is formed over the channel region. A storage medium is formed over the tunnel dielectric material to store electrical charge. The storage medium is disposed between a first interface material and a second interface material, each interface material provides a smoother interface between the storage medium and surrounding dielectric materials. A charge blocking material is formed over the storage medium, followed by a control gate material.

Claims

1. A memory cell, comprising:

a channel region extending between first and second diffusion regions formed in a substrate;

a tunnel dielectric material disposed over the channel region;

a storage medium disposed over the tunnel dielectric material, the storage medium configured to store electrical charge;

a first interface material disposed at the interface between the tunnel dielectric material and the storage medium;

a charge blocking material disposed over the storage medium;

a second interface material disposed at the interface between the charge blocking material and the storage medium; and

a control gate disposed over the charge blocking material.

2. The memory cell of claim 1 wherein the charge blocking material comprises a high K dielectric material.

3. The memory cell of claim 2 wherein the high K dielectric material comprises a material from at least one of lanthanide-based oxides, transition metal-based oxides, oxynitrides, silicates, aluminates, mixed oxides, composites and laminates.

4. The memory cell of claim 3 wherein the high K dielectric material includes at least one of alumina, hafnium silicon oxynitride, and lanthanum aluminum oxide.

5. The memory cell of claim 2 wherein the storage medium comprises a P⁺ doped polysilicon material.

6. The memory cell of claim 2 wherein the first and second interface materials comprise a material of at least one of silicon-nitride, silicon oxy-nitride, silicon-rich nitride and aluminum nitride.

7. A memory cell, comprising:

a channel region extending between first and second diffusion regions formed in a substrate, the first and second diffusion regions being doped with a first material having a first polarity;

a tunnel dielectric material adjacent the channel region;

a storage medium adjacent the tunnel dielectric material, the storage medium being doped with a second material having a second polarity that is opposite of the first polarity, the storage medium configured to store electrical charge;

a charge blocking material adjacent the storage medium; and

a control gate adjacent the charge blocking material.

8. The memory cell of claim 7 wherein the first material comprises N⁺ doped silicon substrate and the second material comprises P⁺ doped polysilicon material.

9. The memory cell of claim 8 wherein the polysilicon material is doped with boron.

10. The memory cell of claim 7 wherein the charge blocking material comprises a high K dielectric material.

11. A memory device, comprising:

an array of memory cells, each of the memory cells in the array comprising;

a source region and a drain region formed in a substrate adjacent opposite ends of a channel region;

a tunnel oxide material formed over the channel region;

a storage medium formed over the tunnel oxide material, the storage medium configurable to store and discharge an electrical charge responsive to an electric field;

a first interface material formed between the tunnel oxide material and the storage medium, the first interface material structured to be resistant to a local electric field at the tunnel oxide and storage medium interface responsive to the electric field;

a charge blocking material formed over the storage medium;

a second interface material formed between the charge blocking material and the storage medium, the second interface material structured to be resistant to a local electric field at the charge blocking material and storage medium interface responsive to the electric field; and

a control gate formed over the charge blocking medium, the control gate operable to receive a bias voltage that generates the electric field.

12. The memory device of claim 11 wherein the charge blocking material comprises a high K dielectric material.

13. The memory device of claim 12 wherein the high K dielectric material comprises a material from at least one of lanthanide-based oxides, transition metal-based oxides, oxynitrides, silicates, aluminates, mixed oxides, composites and laminates.

14. The memory device of claim 13 wherein the high K dielectric material includes at least one of alumina, hafnium silicon oxynitride, and lanthanum aluminum oxide.

15. The memory device of claim 11 wherein the storage medium comprises a P⁺ doped polysilicon material.

16. The memory device of claim 11 wherein the first and second interface materials comprise a layer of at least one of silicon-nitride, silicon oxy-nitride, silicon-rich nitride and aluminum nitride.

17. A processor-based system comprising:

processor circuitry; and

at least one memory device having an array of memory cells, each of the memory cells comprising;

a gate stack having a scalable effective oxide thickness, the gate stack comprising;

a tunnel dielectric material formed over a channel region disposed between source/drain regions;

a storage medium formed over the tunnel dielectric material, the storage medium configurable to store electrical charge;

a first interface material formed between the tunnel dielectric material and the storage medium, the first interface material structured to smooth the interface between the storage medium and the tunnel dielectric material;

a charge blocking material formed over the storage medium;

a second interface material formed between the charge blocking material and the storage medium, the second interface material structured to smooth the interface between the charge blocking material and the storage medium; and

a control gate formed over the charge blocking material.

18. The processor-based system of claim 17 wherein the charge blocking material comprises a high K dielectric material.

19. The processor-based system of claim 17 wherein the floating gate comprises a P⁺ doped polysilicon material.

20. The processor-based system of claim 17 wherein the at least one memory device comprises a flash memory device located in a data storage device.

21. The processor-based system of claim 17 wherein the processor circuitry is coupled to a CMOS imager device.

22. The processor-based system of claim 17 wherein the first and second interface materials comprise a material of at least one of silicon-nitride, silicon oxy-nitride, silicon-rich nitride and aluminum nitride.

26. The method of claim 21 wherein the high K dielectric material comprises a material from at least one of lanthanide-based oxides, transition metal-based oxides, oxynitrides, silicates, aluminates, mixed oxides, composites and laminates.

27. The method of claim 26 wherein the high K dielectric material comprises at least one of alumina, hafnium silicon oxynitride and lanthanum aluminum oxide.

23. A method of forming a memory cell, comprising:

forming first and second diffusion regions in a substrate, the first and second diffusion regions adjacent opposite ends of a channel region in the substrate;

forming a tunnel dielectric material over the channel region with a first dielectric material;

forming a charge storage material over the tunnel dielectric material;

forming a charge blocking material over the charge storage material with a second dielectric material;

forming a first interface material between the charge storage material and the tunnel dielectric material and a second interface material between the charge storage material and the charge blocking material, the first and second interface materials being a high K dielectric material; and

forming a control gate over the charge blocking material.

24. The method of claim 23 wherein forming the charge storage material comprising P⁺ doping the charge storage material with boron.

25. The method of claim 23 wherein forming the first and second interface materials comprise depositing a material of at least one of silicon-nitride, silicon oxy-nitride, silicon-rich nitride and aluminum nitride.

28. A method of operating a memory cell, comprising:

tunneling an electrical charge either to or from a storage medium of the memory cell responsive to an applied programming voltage;

smoothing the interface surrounding the storage medium with a first high K dielectric material; and

doping the storage medium with a material having a polarity opposite to the polarity of at least one material surrounding the storage medium.

29. The method of claim 28 wherein the storage medium is doped with boron.

30. The method of claim 28 wherein smoothing the interface surrounding the storage medium with the first high K dielectric material comprises surrounding the storage medium with a material of at least one of silicon-nitride, silicon oxy-nitride, silicon-rich nitride and aluminum nitride.

31. The method of claim 28 further comprising forming a charge blocking material adjacent to the storage medium, wherein the charge blocking material comprises a second high K material.

32. The method of claim 31 wherein the applied programming voltage is scalable by changing the type of first high K dielectric material and the type of second high K dielectric material.

33. The method of claim 32 wherein the second high K dielectric material comprises at least one of alumina, hafnium silicon oxynitride and lanthanum aluminum oxide.