CORE VOLTAGE DISCHARGE DRIVER

• US 20090067263A1
• Filed: 12/28/2007
• Published: 03/12/2009
• Est. Priority Date: 09/12/2007
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: CHOI, Jun-Gi
• Granted Patent: US 7,586,796 B2
• Time in Patent Office: Days
• US Class Current: 365/189.90
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits

Abstract

A core voltage discharge driver prevents a core voltage discharging operation from interrupting the core voltage generating operation. The core voltage discharge driver includes a comparing unit configured to compare a core voltage generating control signal for controlling generation of a core voltage with a core voltage discharging control signal for controlling discharge of the core voltage, and an adjusting unit configured to adjust the core voltage discharging control signal based on a comparison result of the comparing unit.

Claims

1. A core voltage discharge driver, comprising:

a comparing unit configured to compare a core voltage generating control signal with a core voltage discharging control signal; and

an adjusting unit configured to adjust the core voltage discharging control signal based on a comparison result of the comparing unit.

2. The core voltage discharge driver as recited in claim 1, wherein the comparing unit includes an op-amp configured to receive the core voltage generating control signal and the core voltage discharging control signal.

3. The core voltage discharge driver as recited in claim 2, wherein the op-amp operates according to opening or closing of a current path between external voltage terminals connected to the op-amp by a clamp signal.

4. The core voltage discharge driver as recited in claim 2, wherein the adjusting unit controls the core voltage discharging control signal when a level of the core voltage discharging control signal is higher than a level of the core voltage generating control signal.

5. The core voltage discharge driver as recited in claim 4, wherein the adjusting unit includes a first transistor having a gate terminal configured to receive an output signal of the op-amp and a drain terminal configured to receive the core voltage discharging control signal.

6. The core voltage discharge driver as recited in claim 5, wherein the adjusting unit further includes a second transistor connected between the first transistor and a ground voltage terminal and configured to open and close a current path between the first transistor and the ground voltage terminal.

7. The core voltage discharge driver as recited in claim 6, wherein the adjusting unit further includes a delaying unit configured to delay the output signal of the op-amp, wherein an output signal of the delaying unit is inputted to a gate terminal of the second transistor.

8. The core voltage discharge driver as recited in claim 6, wherein the delaying unit includes:

a first inverter configured with a PMOS transistor and an NMOS transistor connected in series between a power supply voltage terminal and the ground voltage terminal; and

a second inverter configured to invert an output signal of the first inverter.

9. The core voltage discharge driver as recited in claim 7, wherein the first transistor and the second transistor are NMOS transistors.

10. The core voltage discharge driver as recited in claim 9, further comprising a muting unit connected to an output terminal of the op-amp and configured to mute the output signal of the op-amp in response to a clamp signal.

11. A core voltage discharge driver, comprising:

a core voltage generating unit configured to generate a core voltage using an external voltage;

a core voltage discharging unit configured to control discharge of the core voltage by comparing a first reference voltage with the core voltage fed back from the core voltage generating unit; and

a discharge adjusting unit configured to compare a core voltage generating control signal with a core voltage discharging control signal, and to adjust a core voltage discharged in the core voltage discharging unit based on the comparison result.

12. The core voltage discharge driver as recited in claim 11, wherein the core voltage generating unit generates a core voltage using an external voltage when the fed backed core voltage is compared with a second reference voltage and the fed backed core voltage is smaller than the second reference voltage.

13. The core voltage discharge driver as recited in claim 11, wherein the core voltage discharging unit controls the discharge of the core voltage when the fed backed core voltage is compared with the first reference voltage and the fed backed core voltage is larger than the first reference voltage.

14. The core voltage discharge driver as recited in claim 11, wherein the discharge adjusting unit includes:

an op-amp configured to compare the core voltage generating control signal with the core voltage discharging control signal;

an adjuster configured to adjust the core voltage discharging control signal based on a value of an output signal of the op-amp;

a delay configured to delay the output signal of the op-amp to control a current path coupled to the adjuster; and

a muter configured to mute the output signal of the op-amp in response to an external clamp signal.