METHOD OF MANUFACTURING ARRAY SUBSTRATE OF LIQUID CRYSTAL DISPLAY DEVICE

• US 20090068801A1
• Filed: 05/28/2008
• Published: 03/12/2009
• Est. Priority Date: 09/07/2007
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: Song, Youngjin
• Granted Patent: US 8,003,451 B2
• Time in Patent Office: Days
• US Class Current: 438/160
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

The embodiment of the invention discloses an exemplary method, in which a gate line, a gate electrode, and a pixel electrode are formed in a first step; a multilayer structure is formed on the gate line and the gate electrode in a second step; and a data line and source/drain electrodes are formed in a third step.

Claims

1. A method of manufacturing an array substrate of a liquid crystal display (LCD) device, comprising the steps of:

step 1, in which a transparent electrode layer and a gate metal layer are sequentially deposited on a surface of a substrate and are patterned with a first mask plate, so as to form a pixel electrode from the transparent electrode layer and a gate line and a gate electrode branched from the gate line from the gate metal layer;

step 2, in which a gate insulating layer, a semiconductor layer, and a heavily doped semiconductor layer are deposited sequentially on the substrate after step 1 and are patterned with a second mask plate, and the gate insulating layer covers the gate line and the gate electrode, the semiconductor layer and the heavily doped semiconductor layer are remained above the gate electrode, and the gate metal layer is removed on the pixel electrode to expose the pixel electrode; and

step 3, in which a data metal layer is deposited on the substrate after step 2 and is patterned with a third mask plate, so as to form source/drain electrodes and a data line, and the semiconductor layer is exposed in an interval region between the source/drain electrodes.

2. The method of claim 1, wherein the second mask plate is a gray tone mask plate comprising a non-transmissive region, a semi-transmissive region, and a transmissive region, and

wherein the non-transmissive region corresponds to the gate electrode, the semi-transmissive region corresponds to the gate line, and the transmissive region corresponds to the rest region of the substrate,

the heavily doped semiconductor layer, the semiconductor layer, and the gate metal layer corresponding to the transmissive region are removed by a first etching, and the heavily doped semiconductor layer and the semiconductor layer corresponding to the semi-transmissive region are removed by a second etching.

3. The method of claim 1, wherein, in step 3, after patterning with the third mask plate so as to form the source/drain electrodes and the data line, a passive layer is deposited and is removed above the source/drain electrodes and the data line.

4. The method of claim 1, wherein, in step 3, a capacitance electrode is formed from the data metal layer, the capacitance electrode is isolated from the data line and the source/drain electrodes, one end of the capacitance electrode is connected with the pixel electrode, and the other is overlapped on the gate line.

5. The method of claim 1, wherein, in step 1, a common electrode line having the same structure of the gate line is formed and is parallel with the gate line;

in step 2, the common electrode line is covered at least with the gate insulating layer; and

in step 3, a capacitance electrode is formed from the data metal layer, the capacitance electrode is isolated from the data line and the source/drain electrodes, one end of the capacitance electrode is electrically connected with the pixel electrode, and the other is overlapped on the common electrode line.

6. The method of claim 2, wherein, in step 3, after patterning with the third mask plate so as to form the source/drain electrodes and the data line, a passive layer is deposited and is removed above the source/drain electrodes and the data line.

7. The method of claim 6, wherein, in step 3, a capacitance electrode is formed from the data metal layer, the capacitance electrode is isolated from the data line and the source/drain electrodes, one end of the capacitance electrode is connected with the pixel electrode, and the other is overlapped on the gate line.

8. The method of claim 6, wherein, in step 1, a common electrode line having the same structure of the gate line is formed and is parallel with the gate line;

in step 2, the common electrode line is covered at least with the gate insulating layer; and

in step 3, a capacitance electrode is formed from the data metal layer, the capacitance electrode is isolated from the data line and the source/drain electrodes, one end of the capacitance electrode is electrically connected with the pixel electrode, and the other is overlapped on the common electrode line.

9. The method of claim 1, wherein the gate metal layer or the data metal layer comprises a single layer structure formed of a material selected from the group consisting of AlNd, Al, Cu, Mo, MoW, and Cr, or a multilayer structure formed of any combination of AlNd, Al, Cu, Mo, MoW and Cr.

10. The method of claim 1, wherein the gate insulating layer comprises a single layer structure formed of a material selected from the group consisting of SiNx, SiOx and SiOxNy, or a multilayer structure formed of any combination of SiNx, SiOx and SiOxNy.

11. The method of claim 3, wherein the passive layer comprises a single layer structure formed of a material selected from the group consisting of SiNx, SiOx and SiOxNy, or a multilayer structure formed of any combination of SiNx, SiOx and SiOxNy.

12. The method of claim 6, wherein the passive layer comprises a single layer structure formed of a material selected from the group consisting of SiNx, SiOx and SiOxNy, or a multilayer structure formed of any combination of SiNx, SiOx and SiOxNy.

13. The method of claim 2, wherein, in step 3, a capacitance electrode is formed from the data metal layer, the capacitance electrode is isolated from the data line and the source/drain electrodes, one end of the capacitance electrode is connected with the pixel electrode, and the other is overlapped on the gate line.

14. The method of claim 3, wherein, in step 3, a capacitance electrode is formed from the data metal layer, the capacitance electrode is isolated from the data line and the source/drain electrodes, one end of the capacitance electrode is connected with the pixel electrode, and the other is overlapped on the gate line.

15. The method of claim 2, wherein, in step 1, a common electrode line having the same structure of the gate line is formed and is parallel with the gate line;

in step 2, the common electrode line is covered at least with the gate insulating layer; and

in step 3, a capacitance electrode is formed from the data metal layer, the capacitance electrode is isolated from the data line and the source/drain electrodes, one end of the capacitance electrode is electrically connected with the pixel electrode, and the other is overlapped on the common electrode line.

16. The method of claim 3, wherein, in step 1, a common electrode line having the same structure of the gate line is formed and is parallel with the gate line;

in step 2, the common electrode line is covered at least with the gate insulating layer; and

in step 3, a capacitance electrode is formed from the data metal layer, the capacitance electrode is isolated from the data line and the source/drain electrodes, one end of the capacitance electrode is electrically connected with the pixel electrode, and the other is overlapped on the common electrode line.