DUAL WORK FUNCTION CMOS DEVICES UTILIZING CARBIDE BASED ELECTRODES

• US 20090068828A1
• Filed: 11/14/2008
• Published: 03/12/2009
• Est. Priority Date: 08/15/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chambers, James Joseph, Colombo, Luigi, Visokay, Mark Robert
• Granted Patent: US 7,842,567 B2
• Time in Patent Office: Days
• US Class Current: 438/592
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence

Abstract

Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region.

Claims

1. A method of forming metal gate transistors, comprising:

forming a layer of metal nitride material over a dielectric layer overlying a semiconductor substrate, the metal nitride having a first work function;

selectively masking off the metal nitride so that the metal nitride is covered in a first region and exposed in a second region;

adding at least one of oxygen and carbon to the exposed metal nitride in the second region to establish a second work function in the second region;

forming a layer of polysilicon material over the first and second regions; and

forming one or more first transistor types in the first region and one or more second transistor types in the second region.

2. The method of claim 1, wherein at least one of:

the first metal comprises at least one of TaN and TiN,

adding at least one of oxygen and carbon facilitates establishing at least one of metal oxy nitride, metal carbide nitride or metal oxy carbide nitride in the second region,

the first work function is between about 3.5 eV and about 4.3 eV,

the second work function is between about 4.8 eV and about 5.5 eV,

the first metal is selectively masked off with a patterned layer of a capping material,

the dielectric has a thickness of less than about 5 nanometers,

the dielectric comprises at least one of silicon oxynitride (SiON) and a high k dielectric material,

the at least one of oxygen and carbon are added by at least one of thermal, plasma and implantation processing, and

the polysilicon is formed to a thickness of about a few hundred nanometers or less.

3. The method of claim 2, wherein the layer of capping material comprises silicon.

4. The method of claim 1, further comprising:

forming barrier material over the first and second regions before the polysilicon is formed.

5. The method of claim 4, wherein the barrier material comprises at least one of TiN and TaN.