METHOD AND APPARATUS FOR CASCADE MEMORY

• US 20090070522A1
• Filed: 08/11/2008
• Published: 03/12/2009
• Est. Priority Date: 02/27/2006
• Status: Active Grant

• Current Assignee: Trek 2000 International Limited (Trek Technology Singapore PTE Limited)
• Original Assignee: Trek 2000 International Limited (Trek Technology Singapore PTE Limited)
• Inventors: Poo, Teng Pin
• Granted Patent: US 8,443,132 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A system and method of operating a cascade of a plurality of memory devices connected in series is disclosed. In one aspect, there is a memory controller operatively connected to the memory cell and a cascade circuit configured to enable a subsequent memory device in a cascade of memory devices.

Claims

1. A memory device comprising:

(a) a memory cell;

(b) a memory controller operatively connected to the memory cell; and

(c) a cascade circuit configured to enable a subsequent memory device in a cascade of memory devices, wherein the cascade circuit is operatively connected to the memory controller and for controlling a pin-out-to-chip.

2. The memory device as claimed in claim 1, wherein the cascade circuit is further configured to enable the subsequent memory device.

3. The memory device as claimed in claim 1, wherein the subsequent memory device is configured to be enabled only when the memory device has concluded writing data to, or reading data from, the memory cell.

4. The memory device as claimed in claim 1, further comprising a device enable input operatively connected to the memory controller.

5. The memory device as claimed in any one of claims 1, wherein the memory device comprises a non-volatile, solid-state memory device.

6. A method of operating a cascade of a plurality of memory devices connected in series, the method comprising:

(a) enabling a first memory device with a microcontroller, wherein the microcontroller comprises a single chip-select pin and connect for enabling the plurality of memory devices; and

(b) enabling, at the first memory device, a subsequent memory device in the cascade of memory devices connected in series to the first memory device.

7. A method as claimed in claim 6, wherein the single chip-select pin and connect are operatively connected to a device enable input of the first memory device and wherein the device enable input is operatively connected to a memory controller of the first memory device.

8. A method as claimed in claim 6, wherein the first memory device comprises a single pin-out-to-chip and connect operatively connected to the subsequent memory device at the second memory device'"'"'s device enable input.

9. A method as claimed in claim 6, wherein the single pin-out-to-chip is controlled by a cascade circuit that is operatively connected to the memory controller and the pin-out-to-chip.

10. A method as claimed in claim 6, wherein the cascade circuit is configured to determine when to enable the subsequent memory device based on data from the memory controller.

11. A method as claimed in claim 6, wherein the subsequent memory device is able to be enabled only when the memory device has concluded writing data to, or reading data from, the memory cell.

12. A memory device comprising:

(a) a memory cell;

(b) a memory controller operatively connected to the memory cell; and

(c) a cascade circuit operatively connected to the memory controller, wherein the cascade circuit is configured to enable a subsequent memory device in a cascade of memory devices and wherein the cascade circuit is configured to determine when to enable the subsequent memory device based on data from the memory controller.

13. A memory device comprising:

(a) a memory cell;

(b) a memory controller operatively connected to the memory cell; and

(c) a cascade circuit operatively connected to the memory controller, the cascade circuit configured to enable a subsequent memory device in a cascade of memory devices wherein the subsequent memory device is configured to be enabled only when the memory device has concluded writing data to, or reading data from, the memory cell.

14. A method of operating a cascade of a plurality of memory devices connected in series, the method comprising:

(a) enabling a first memory device with a microcontroller; and

(b) enabling a subsequent memory device in the cascade of memory devices connected in series to the first memory device wherein the first memory device comprises a memory cell, wherein a memory controller is operatively connected to the memory cell, and wherein a cascade circuit is operatively connected to the memory controller, and wherein the cascade circuit is configured to determine when to enable the subsequent memory device based on data from the memory controller.

15. A method of operating a cascade of a plurality of memory devices connected in series, the method comprising:

(a) enabling a first memory device with a microcontroller; and

(b) enabling a subsequent memory device in the cascade of memory devices connected in series to the first memory device, wherein the first memory device comprises a memory cell, wherein a memory controller is operatively connected to the memory cell, and wherein a cascade circuit is operatively connected to the memory controller, wherein the subsequent memory device is configured to be enabled only when the memory device has concluded writing data to, or reading data from, the memory cell.