DISPATCH MECHANISM FOR DISPATCHING INSTURCTIONS FROM A HOST PROCESSOR TO A CO-PROCESSOR

• US 20090070553A1
• Filed: 09/12/2007
• Published: 03/12/2009
• Est. Priority Date: 09/12/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Convey Computer
• Inventors: Wallach, Steven J., Brewer, Tony
• Granted Patent: US 8,122,229 B2
• Time in Patent Office: Days
• US Class Current: 712/34
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

A dispatch mechanism is provided for dispatching instructions of an executable from a host processor to a heterogeneous co-processor. According to certain embodiments, cache coherency is maintained between the host processor and the heterogeneous co-processor, and such cache coherency is leveraged for dispatching instructions of an executable that are to be processed by the co-processor. For instance, in certain embodiments, a designated portion of memory (e.g., “UCB”) is utilized, wherein a host processor may place information in such UCB and the co-processor can retrieve information from the UCB (and vice-versa). The UCB may thus be used to dispatch instructions of an executable for processing by the co-processor. In certain embodiments, the co-processor may comprise dynamically reconfigurable logic which enables the co-processor'"'"'s instruction set to be dynamically changed, and the dispatching operation may identify one of a plurality of predefined instruction sets to be loaded onto the co-processor.

Claims

1. A method for dispatching instructions of an executable image from a host processor to a heterogeneous co-processor in a multi-processor system, wherein said host processor and said heterogeneous co-processor have different instruction sets, the method comprising:

writing, by said host processor, an address of instructions of said executable image to a designated portion of memory;

detecting, by said co-processor, said address of said instructions in the designated portion of memory; and

executing, by said co-processor, said instructions.

2. The method of claim 1 further comprising:

addressing, by said host processor, said designated portion of memory by a virtual address; and

addressing, by said co-processor, said designated portion of memory by said virtual address.

3. The method of claim 1 wherein said address of said instructions comprises a global virtual address, said method further comprising accessing said designated portion of memory by said host processor and by said co-processor, wherein said accessing comprises:

generating said global virtual address;

translating the global virtual address into a global physical address; and

maintaining cache coherency between said host processor and said co-processor to ensure that an up-to-date value of the designated portion of memory is accessed.

4. The method of claim 1 wherein said host processor and said co-processor share a common global virtual address space;

and wherein said host processor and said co-processor share a common global physical address space.

5. The method of claim 1 further comprising:

writing one instruction at a time by said host processor to said designated portion of memory.

6. The method of claim 1 wherein said writing said address of said instructions to said designated portion of memory comprises:

writing an address for a first instruction of a block of instructions by the host processor to said designated portion of memory.

7. The method of claim 1 wherein said writing said instructions to said designated portion of memory comprises:

instructing, by an operating system running on the host processor, an input/output (I/O) system to read said instructions from disk and write said instructions to said designated portion of memory.

8. The method of claim 1 wherein said detecting, by said co-processor, comprises:

monitoring, by the co-processor, a value in an issue memory structure;

detecting, by the co-processor, a predefined value in said issue memory structure that is indicative of said instructions at said address written in the designated portion of memory are ready for execution by said co-processor;

after writing said address of the instructions of said executable image to the designated portion of memory, writing, by the host processor, the predefined value to the issue memory structure for triggering processing of the instructions by the co-processor; and

responsive to detecting said predefined value in the issue memory structure, said co-processor performing said executing of said instructions at said address written in the designated portion of memory.

9. The method of claim 8 wherein the designated portion of memory comprises a command memory structure, the method further comprising:

writing information to said issue memory structure to indicate that the host processor possesses ownership of the command memory structure prior to said host processor writing said address of said instructions of said executable image to said command memory structure;

writing said information to said issue memory structure to indicate that the co-processor possesses ownership of the command memory structure after said host processor writing said address of said instructions of said executable image to said command memory structure and prior to said co-processor executing said instructions; and

writing said information to said issue memory structure to indicate that the host processor possesses ownership of the command memory structure after said co-processor executing said instructions.

10. The method of claim 9 further comprising:

monitoring, by said co-processor, cache coherency requests sent from the host processor to the co-processor for said issue memory structure.

11. The method of claim 1 wherein said co-processor comprises reconfigurable logic for dynamically reconfiguring the co-processor'"'"'s instruction set to be any of a plurality of predefined processor instruction sets, said method further comprising:

writing information to said designated portion of memory to specify one of the plurality of predefined processor instruction sets to be employed on the co-processor for processing the instructions.

12. A method for issuing instructions of an executable file for processing by a co-processor, the method comprising:

monitoring, by the co-processor, an issue memory structure;

writing, by a host processor, to a command memory structure an address of instructions of the executable file to be processed by the co-processor;

writing, by the host processor, a predefined value to the issue memory structure for triggering processing of the instructions; and

responsive to detecting said predefined value in the issue memory structure, said co-processor processing the instructions of the executable file.

13. The method of claim 12 wherein the co-processor comprises a different instruction set than said host processor, the method further comprising:

maintaining cache coherency between said co-processor and said host processor.

14. The method of claim 12 wherein said issue memory structure comprises information indicating whether current ownership of the command memory structure is possessed by said host processor or by said co-processor, the method further comprises:

writing, by said host processor, said information to said issue memory structure to indicate that the host processor possesses ownership of the command memory structure prior to said host processor writing said address of said instructions of said executable file to said command memory structure;

writing said information to said issue memory structure to indicate that the co-processor possesses ownership of the command memory structure after said host processor writing said address of said instructions of said executable file to said command memory structure and prior to said co-processor executing said instructions; and

writing said information to said issue memory structure to indicate that the host processor possesses ownership of the command memory structure after said co-processor executing said instructions.

15. The method of claim 12 wherein said monitoring said issue memory structure comprises:

monitoring, by said co-processor, cache line activity of the issue memory structure; and

responsive to detecting cache line activity occurring in the issue memory structure, said co-processor determining whether the issue memory structure contains said predefined value for triggering processing of the instructions addressed at the address in the command memory structure.

16. The method of claim 12 further comprising:

initializing registers of the co-processor, wherein said initializing comprises writing data to said registers of the co-processor from said command memory structure.

17. The method of claim 12 wherein said co-processor comprises reconfigurable logic for dynamically reconfiguring the co-processor'"'"'s instruction set to be any of a plurality of predefined processor instruction sets, said method further comprising:

writing, by said host processor, information to said command memory structure to specify one of the plurality of predefined processor instruction sets to be employed on the co-processor for processing the instructions.

18. A method comprising:

processing instructions of an executable image by a multi-processor system that comprises a host processor having a first instruction set and a heterogeneous co-processor having a second instruction set that is different than said first instruction set, wherein the executable image comprises at least one segment of instructions for the first instruction set and at least one segment of instructions for the second instruction set;

maintaining cache coherency between the at least one host processor and the at least one heterogeneous co-processor;

writing to a command memory structure, by the host processor, a virtual address of a first instruction of the at least one segment of instructions for the second instruction set; and

triggering the co-processor to begin execution of said at least one segment of instructions for the second instruction set at the virtual address by said host processor writing a value to an issue memory structure.

19. The method of claim 18 further comprising:

upon initiating said executable image for processing by said multi-processor system, loading said instructions of said executable image into memory.

20. The method of claim 18 wherein the heterogeneous co-processor comprises dynamically reconfigurable logic, the method comprising:

configuring said dynamically reconfigurable logic to have said second instruction set.

21. A multi-processor system comprising:

a plurality of processors comprising at least a host processor and a heterogeneous co-processor, wherein the host processor and heterogeneous co-processor each process a portion of instructions of an executable file;

a command memory structure to which said host processor identifies instructions of the executable file that are to be processed by the co-processor; and

an issue memory structure that indicates which of said plurality of processors possesses ownership of said command memory structure.

22. The multi-processor system of claim 21 wherein said host processor writes a predefined value to the issue memory structure for triggering processing of the instructions identified in the command memory structure by the heterogeneous co-processor, and wherein said co-heterogeneous co-processor monitors the issue memory structure, and responsive to detecting said predefined value in the issue memory structure, said co-processor processes the instructions of the executable file that are identified in the command memory structure.

23. The multi-processor system of claim 22 wherein said host processor and said heterogeneous co-processor each comprise respective local caches, and wherein cache coherency is maintained between said host processor and said heterogeneous co-processor;

wherein said heterogeneous co-processor monitors cache line activity of the issue memory structure to detect information being written to the issue memory structure indicating that ownership of the command memory structure has changed to be possessed by the co-processor, wherein responsive to detecting said information in the issue memory structure, said co-processor processes the instructions of the executable file that are in the command memory structure.

24. The multi-processor system of claim 21 wherein said co-processor comprises reconfigurable logic for dynamically reconfiguring the co-processor'"'"'s instruction set to be any of a plurality of predefined processor instruction sets, wherein said host processor writes information to said command memory structure to specify one of the plurality of predefined processor instruction sets to be employed on the co-processor for processing the instructions.

25. A multi-processor system comprising:

at least one host processor having a first instruction set and comprising a first main memory;

at least one heterogeneous co-processor having a second instruction set that is different than said first instruction set and comprising a second main memory, wherein said first main memory and said second main memory are in a common global physical memory space;

said at least one host processor and said at least one heterogeneous co-processor each comprising a respective local cache, wherein cache coherency is maintained between the at least one host processor and at least one heterogeneous co-processor; and

a designated portion of at least one of said first main memory and said second main memory to which the at least one host processor stores identification of instructions of an executable for processing by said at least one heterogeneous co-processor.