Computation parallelization in software reconfigurable all digital phase lock loop

• US 20090070568A1
• Filed: 12/03/2007
• Published: 03/12/2009
• Est. Priority Date: 09/11/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Staszewski, Roman, Staszewski, Robert B., Shi, Fuqiang
• Granted Patent: US 7,809,927 B2
• Time in Patent Office: Days
• US Class Current: 712/237
• CPC Class Codes: G06F 9/30003 Arrangements for executing specific machine instructions
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/3875 Pipelining a single stage, e.g. superpipelining
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/1806 the frequency divider comprising a phase accumulator generating the frequency divided signal
• CPC Class Codes: H03L 7/1974 for fractional frequency division

Abstract

A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. A multi-stage data stream based processor incorporates a parallel/pipelined architecture optimized to perform data stream processing efficiently. The multi-stage parallel/pipelined processor provides significantly higher processing speeds by combining multiple RCUs wherein input data samples are input in parallel to all RCUs while computation results from one RCU are used by adjacent downstream RCUs. A register file provides storage for historical values while local storage in each RCU provides storage for temporary results.

Claims

1. A processor, comprising:

a plurality of reconfigurable calculation units coupled both in parallel wherein input data samples are fed in parallel thereto and in a pipelined configuration wherein results from one reconfigurable calculation unit are input to a reconfigurable calculation unit adjacent thereto;

each reconfigurable calculation unit comprising;

a feedback path operative to perform sequential functional processing of data samples;

a forward path operative to transfer processing results between adjacent reconfigurable calculation units; and

a register file operative to store historical result values generated by a last reconfigurable calculation unit in said pipeline;

2. The processor according to claim 1, wherein each reconfigurable calculation unit comprises local registers for storing temporary computation results.

3. The processor according to claim 1, wherein only a first reconfigurable calculation unit reads previously written result data from said register file.

4. The processor according to claim 1, wherein an input data sample is processed in a single reconfigurable calculation unit.

5. The processor according to claim 1, wherein a downstream processing reconfigurable calculation unit is operative to process a same processing function processed by an upstream reconfigurable calculation unit adjacent thereto in a previous cycle.

6. The processor according to claim 1, wherein a downstream processing reconfigurable calculation unit is operative to utilize a historical value output by an upstream reconfigurable calculation unit adjacent thereto in a previous cycle.

7. The processor according to claim 1, wherein each reconfigurable calculation unit utilizes its own output as input for a subsequent processing function.

8. The processor according to claim 1, further comprising an instruction decoder operative to generate the same control and configuration signals for each reconfigurable calculation unit but with a pipelined delay therebetween.

9. A data stream processor, comprising:

a plurality of reconfigurable calculation units coupled both in parallel and in a pipelined configuration wherein input data samples are fed in parallel to said reconfigurable calculation units and processed in a pipelined manner for all processing functions;

each reconfigurable calculation unit comprising;

a feedback path operative to perform sequential functional processing of said input data samples;

a forward path operative to transfer processing results between adjacent reconfigurable calculation units;

a loopback path operative to support forking and merging operations; and

a register file operative to store historical result values generated by a last reconfigurable calculation unit in said pipeline.

10. The processor according to claim 9, wherein said loopback path comprises one or more latches coupling a reconfigurable calculation unit output to its input thereby latching results for forking and merging operations.

11. The processor according to claim 9, wherein each reconfigurable calculation unit comprises local registers for storing temporary computation results.

12. The processor according to claim 9, wherein only a first reconfigurable calculation unit reads previously written result data from said register file.

13. The processor according to claim 9, wherein an input data sample is processed in a single reconfigurable calculation unit.

14. The processor according to claim 9, wherein a downstream processing reconfigurable calculation unit is operative to process a same processing function processed by an upstream reconfigurable calculation unit logically adjacent thereto in a previous cycle.

15. The processor according to claim 9, wherein a downstream processing reconfigurable calculation unit is operative to utilize a historical value output by an upstream reconfigurable calculation unit logically adjacent thereto in a previous cycle.

16. The processor according to claim 9, wherein each reconfigurable calculation unit utilizes its own output as input for a subsequent processing function after processing a new input sample data.

17. The processor according to claim 9, further comprising an instruction decoder operative to generate the same control and configuration signals for each reconfigurable calculation unit but with a pipelined delay therebetween.

18. A data stream processing method, said method comprising the steps of:

coupling a plurality of reconfigurable calculation units coupled both in parallel and in a pipelined configuration, feeding input data samples in parallel to said reconfigurable calculation units and processing them in a pipelined manner for all processing functions;

performing sequential functional processing of said input data samples in a sequential path within each reconfigurable calculation unit; and

transferring processing results between adjacent reconfigurable calculation units.

19. The processing method according to claim 18, further comprising the step of performing forking and merging operations using a loopback path in each reconfigurable calculation unit.

20. The processing method according to claim 18, further comprising the step of reading historical results values from a register file by a first reconfigurable calculation unit and writing results values to said register file by a last reconfigurable calculation unit.

21. A processor based phase locked loop (PLL), comprising:

an oscillator operative to generate a radio frequency (RF) signal having a frequency determined in accordance with a tuning command input thereto;

a processor operative to generate said tuning command comprising a plurality of reconfigurable calculation units coupled both in parallel and in a pipelined configuration wherein input data samples are fed alternately to said reconfigurable calculation units and processed in a pipelined manner for all processing functions; and

program memory coupled to said reconfigurable calculation unit for storing a plurality of instructions that when executed on said processor implement said phase locked loop.

22. The phase locked loop according to claim 21, wherein each reconfigurable calculation unit comprises a loopback path operative to support forking and merging operations.

23. The phase locked loop according to claim 21, wherein an input data sample is processed in a single reconfigurable calculation unit.

24. A radio, comprising:

a transmitter coupled to an antenna, said transmitter comprising a software based phase locked loop (PLL), said phase locked loop comprising;

an oscillator operative to generate a radio frequency (RF) signal having a frequency determined in accordance with a tuning command input thereto;

a processor operative to generate said tuning command, said processor comprising;

a plurality of reconfigurable calculation units coupled both in parallel and in a pipelined configuration wherein input data samples are fed in parallel to said reconfigurable calculation units and processed in a pipelined manner for all processing functions;

each reconfigurable calculation unit operative to perform atomic operations required to implement said phase locked loop and comprising;

a feedback path operative to perform sequential functional processing of data samples;

a forward path operative to transfer processing results between adjacent reconfigurable calculation units;

a loopback path operative to support forking and merging operations;

a register file communicatively coupled to a first reconfigurable calculation unit and a last reconfigurable calculation unit;

program memory coupled to said reconfigurable calculation unit for storing a plurality of instructions that when executed on said processor implement said phase locked loop;

said processor having an instruction set, wherein each instruction is operative to perform an atomic operation of said phase locked loop;

a receiver coupled to said antenna; and

a baseband processor coupled to said transmitter and said receiver.

25. The radio according to claim 24, wherein each reconfigurable calculation unit comprises a loopback path operative to support forking and merging operations.