Method for Providing a Cluster-Wide System Clock in a Multi-Tiered Full-Graph Interconnect Architecture
First Claim
1. A method, in a computing cluster comprising a plurality of processor chips, for providing a cluster-wide system clock signal, comprising:
- synchronizing heartbeat signals transmitted by each of the processor chips in the plurality of processor chips such that each processor chip in the plurality of processor chips transmits a heartbeat signal at approximately a same time; and
generating, in each processor chip of the plurality of processor chips, an internal system clock signal based on a heartbeat signal transmitted by the processor chip, wherein through synchronization of the heartbeat signals the internal system clock signals of each processor chip of the plurality of processor chips are synchronized.
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Abstract
A method for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.
174 Citations
20 Claims
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1. A method, in a computing cluster comprising a plurality of processor chips, for providing a cluster-wide system clock signal, comprising:
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synchronizing heartbeat signals transmitted by each of the processor chips in the plurality of processor chips such that each processor chip in the plurality of processor chips transmits a heartbeat signal at approximately a same time; and generating, in each processor chip of the plurality of processor chips, an internal system clock signal based on a heartbeat signal transmitted by the processor chip, wherein through synchronization of the heartbeat signals the internal system clock signals of each processor chip of the plurality of processor chips are synchronized. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A computer program product comprising a computer useable medium having a computer readable program, wherein the computer readable program, when executed in a data processing system, causes the data processing system to:
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synchronize heartbeat signals transmitted by each processor chip in a plurality of processor chips such that each processor chip in the plurality of processor chips transmits a heartbeat signal at approximately a same time; and generates, in each processor chip of the plurality of processor chips, an internal system clock signal based on a heartbeat signal transmitted by the processor chip, wherein through synchronization of the heartbeat signals the internal system clock signals of each processor chip of the plurality of processor chips are synchronized. - View Dependent Claims (19, 20)
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Specification