Three dimensional memory in a system on a chip

• US 20090070721A1
• Filed: 09/12/2008
• Published: 03/12/2009
• Est. Priority Date: 09/12/2007
• Status: Active Grant

• Current Assignee: Solomon Research LLC
• Original Assignee: Solomon Research LLC
• Inventors: Solomon, Neal
• Granted Patent: US 8,042,082 B2
• Time in Patent Office: Days
• US Class Current: 716/118
• CPC Class Codes: G06F 2115/06 Structured ASICs
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A 3D memory management system is described involving (a) memory hierarchy with adjustable synchronous DRAM, (b) 3D active memory with integrated logic circuitry, cache and router, (c) reconfigurable memory, (d) adaptive queue processing, (e) data compression processing and (f) multiple memory components in hierarchical configurations.

Claims

1. A system for organizing multilayer integrated circuit (IC) memory components in a 3D system on a chip (SoC), comprising:

memory components on a layer of a multilayer IC;

wherein the memory components are used by microprocessors, FPGAs or ASICs; and

wherein when the memory components store data and instructions, they are accessed by the logic devices.

2. A system of claim 1, wherein:

The memory components are on multiple layers of 3D IC nodes in the 3D SoC; and

The memory components are on multiple tiles on layers of the 3D IC nodes.

3. A system of claim 1, wherein:

The memory components are accessed by logic devices on layers within 3D IC nodes in the 3D SoC; and

The memory components are accessed by logic devices on layers of other 3D IC nodes in the 3D SoC.

4. A system of claim 1, wherein:

The sequence of access to data and instructions in the multiple memory components from logic devices changes as the applications and problem solving analyses change.

5. A system of claim 1, wherein:

The memory components are assigned to specific neighborhood clusters in the 3D SoC; and

When the neighborhood clusters are reconfigured the memory components on the tiles and layers of the 3D IC nodes rearrange the position of the data sets by reassigning the data to different memory components and tagging and tracking the changes and storing the location changes in databases of the various 3D IC nodes.

6. A system of claim 1, wherein:

The 3D SoC uses multiple pipelines to store and access data in the memory components simultaneously in multiple locations; and

The data are pre-fetched to allocate them to specific memory module locations by anticipating the reconfiguration of the neighborhood clusters for different application types.

7. A system of claim 1, wherein:

Data is transferred between tiles on the same layer of a memory IC;

Data is transferred between tiles on different layers of a memory IC;

Data is transferred between tiles on different layers of different memory ICs;

Data is transferred between tiles on different memory layers of different hybrid logic ICs;

Data is transferred between tiles on different layers of memory ICs and hybrid logic ICs; and

The data transfer occurs between multiple tiles simultaneously.

8. A system for organizing multiple memory types in an integrated memory circuit (IC) in a 3D system on a chip (SoC), comprising:

multiple differentiated memory components on a layer of a multilayer IC;

wherein the memory components are SRAM and DRAM types;

wherein the memory components are arranged with different access corridors;

wherein different logic functions access different memory types simultaneously; and

wherein the multiple memory types are accessed by FPGAs, ASICs and microprocessors on layers of 3D nodes in the 3D SoC.

9. A system of claim 8, wherein:

The FPGA layers access SRAM components in the integrated memory circuit while the microprocessor layers access DRAM components in the integrated memory circuit.

10. A system of claim 8, wherein:

Data in data streams are tagged for identification in a 3D iSoC;

Multiple pipelines in 3D SoC are simultaneously active;

Data tags are forwarded to a central registry;

Data tags update a central database;

When the system engages in a reconfiguration of its evolvable hardware, the memory system reprioritizes and new data tags refer to new data locations; and

The registry is updated with new locations of data in the memory system.

11. A system of claim 8, wherein:

A 3D memory module interacts with 3D IC nodes that contain microprocessor and FPGA layers;

A 3D memory module with integrated memory layers are accessed simultaneously by MP and FPGA layers;

Data is stored in multiple memory layers of a 3D memory module using parallel pipelines;

Patterns of multiple pipelines shift to different memory type tiles in multiple memory layers;

3D memory dynamics in a 3D iSoC continually shift as logic components reconfigure; and

Patterns of data flows in integrated memory module are remodulated.