Three dimensional integrated circuits and methods of fabrication

• US 20090070727A1
• Filed: 09/12/2008
• Published: 03/12/2009
• Est. Priority Date: 09/12/2007
• Status: Active Grant

• Current Assignee: Solomon Research LLC
• Original Assignee: Solomon Research LLC
• Inventors: Solomon, Neal
• Granted Patent: US 8,136,071 B2
• Time in Patent Office: Days
• US Class Current: 716/128
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Three dimensional integrated circuitry is described with applications to hybrid multiprocessor and reconfigurable computing. Methods of fabrication of multilayer ICs are shown using multilayer TSVs.

Claims

1. A system for organizing semiconductor integrated circuits (ICs) into a set of layers of circuits with through silicon vias (TSVs), comprising:

Combining several layers of ICs in a multi-layer module;

Positioning TSVs connecting adjacent layers;

Connecting three or more layers with contiguous TSVs;

Wherein electronic signals are transmitted through the TSVs from one layer of the multilayer module to other layers; and

Wherein the multilayer IC performs specific computational tasks.

2. A system of claim 1, wherein:

Each layer of the multi-layer IC contains multiple individual tiles which are structured to perform specific functions; and

The tiles are connected by interconnects and TSVs.

3. A system of claim 1, wherein:

The layers in the multi-layer IC are microprocessors.

4. A system of claim 1, wherein:

The layers in the multi-layer IC are complex programmable logic devices.

5. A system of claim 1, wherein:

The layers in the multi-layer IC are memory components.

6. A system of claim 1, wherein:

The TSVs in a multi-layer IC are integrated using an inverted pyramid structure that connects layers of the device.

7. A system for organizing semiconductor integrated circuits (ICs) into a set of layers of circuits with through silicon vias (TSVs), comprising:

Combining several layers of ICs in a multi-layer module; and

The multi-layer node is a hybrid IC device consisting of FPGAs, microprocessors and memory components.

8. A system of claim 7, wherein:

The multilayer IC contains FPGA, microprocessor and memory components on tiles on specific layers of the device;

Wherein the interconnection between the tiles on the layers of different computational devices are connected by TSVs.

9. A system for constructing a multi-layer integrated circuit, comprising:

Combining three IC layers in a sandwich assembly;

Applying plasma gas to the IC layer assembly;

Etching specific holes in the top layer of the assembly;

Filling in the holes with metals; and

Adding an IC layer to the etched layer.