IP cores in reconfigurable three dimensional integrated circuits

• US 20090070728A1
• Filed: 09/12/2008
• Published: 03/12/2009
• Est. Priority Date: 09/12/2007
• Status: Active Grant

• Current Assignee: Solomon Research LLC
• Original Assignee: Solomon Research LLC
• Inventors: Solomon, Neal
• Granted Patent: US 8,046,727 B2
• Time in Patent Office: Days
• US Class Current: 716/128
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

The invention describes IP cores applied to 3D FPGAs, CPLDs and reprogrammable SoCs. IP cores are (a) used for continuously evolvable hardware using 3D logic circuits, (b) applied with optimization metaheuristic algorithms, (c) applied by matching combinatorial logic of netlists generated by Boolean algebra to combinatorial geometry of CPLD architecture by reaggregating IP core elements and (d) continuous recalibration of IP cores with evolvable hardware in indeterministic environments for co-evolutionary reprogrammability.

Claims

1. A system for organizing IP cores in three dimensional FPGAs in a three dimensional system on a chip, comprising:

a multi-layer FPGA;

a multi-layer hybrid IC;

SRAM memory components on at least one FPGA layer;

LUTs in FPGA SRAM components;

soft IP cores;

wherein the IP cores include netlists;

wherein at least one IP core accesses a memory component to change the FPGA layer program code;

wherein the IP core program code is forwarded to a switch matrix apparatus on a FPGA layer;

wherein the IP core program code activates at least one logic block array on a FPGA layer tile to reconfigure its interconnects from one ASIC position to another ASIC position when specific criteria are satisfied; and

wherein when the FPGA layer in at least one logic block array are activated, they change their interconnection configuration to a new geometric position.

2. The system of claim 1, wherein:

At least two IP core activates at least two FPGA layer components simultaneously; and

At least two FPGA layers activate the logic block arrays to reconfigure the interconnect configuration to a new geometric position.

3. The system of claim 1, wherein:

When the environment changes, the 3D SoC using modeling processes to solve evolving MOOPs;

The solutions to the MOOPs are input into IP cores to update the program code;

The program code of the updated IP cores is applied to at least one FPGA layer in a multi-layer FPGA or a multi-layer hybrid IC.

4. The system of claim 1, wherein:

IP cores are organized in an IP core library;

The IP core library stores IP cores used to solve MOOPs; and

IP cores are accessed from the IP core library to forward IP cores to at least one FPGA layer in a multi-layer FPGA or multi-layer hybrid IC.

5. A system for organizing IP cores in three dimensional FPGAs in a three dimensional system on a chip, comprising:

a multi-layer FPGA;

a multi-layer hybrid IC;

SRAM memory components on at least one FPGA layer;

LUTs in FPGA SRAM components;

soft IP cores including netlists;

wherein at least one IP core accesses a memory component to change the FPGA layer program code;

wherein IP cores are constructed from IP core elements;

wherein the IP core elements are modular components of program code for specific applications;

wherein the IP core elements are combined into specific customized IP cores to solve specific MOOPs;

wherein the aggregation of IP core elements is organized to apply to at least one layer in a multi-layer FPGA or multi-layer hybrid IC to reconfigure at least one logic block array to a specific geometrical configuration; and

wherein the IP core elements are reaggregated into different multiple combinations for specific applications.

6. A system of claim 5, wherein:

the aggregated IP core elements are applied to specific device type applications of image structure sensor structures, MAC structures, ATSC protocols, wireless communications protocols and embedded controller protocols.

7. A system of claim 5, wherein:

the aggregated IP core elements are applied to specific tiles of specific layers of multi-layer FPGAs.

8. A system of claim 5, wherein:

Multiple aggregated IP core elements are applied to tiles of at least two layers of a multilayer FPGA.

9. A system of claim 5, wherein:

The IP core elements are aggregated as a result of a process of solving MOOPs;

The IP core elements are combined into a unique configuration to solve MOOPs;

A modeling process generates and tests multiple scenarios to develop a solution to MOOPs in an evolving environment;

The modeling system forwards the solution to the MOOPs to the D-EDA system for layout of placement and routing of specific FPGA layers of logic block array interconnects to specific configurations;

The aggregated IP core elements are applied to specific tiles on at least one layer of a multi-layer FPGA to restructure program code to activate a specific placement and route configuration of interconnects within at least one logic block array; and

The logic block array interconnects reconfigure the geometry of their structure.

10. A system for organizing IP cores in three dimensional FPGAs in a three dimensional system on a chip, comprising:

a multi-layer FPGA;

a multi-layer hybrid IC;

SRAM memory components on at least one FPGA layer;

LUTs in FPGA SRAM components soft IP cores including netlists;

wherein at least one IP core accesses a memory component to change the FPGA layer program code;

wherein the evolving environment changes a position, it presents a set of MOOPs to the 3D SoC;

wherein the environment provides feedback to the multi-layer FPGA as they interact;

wherein the 3D SoC models multiple scenarios and solution options and applies the solution options to evolutionary IP cores;

wherein the evolutionary IP cores are applied to the multi-layer FPGA; and

wherein the multi-layer FPGA continuously transforms its geometrical configuration to adapt to the evolving environmental changes.

11. A system of claim 10, wherein:

IP core elements are aggregated and reaggregated over multiple phases to apply changes of configuration to the multiple layers of the multi-layer FPGA.