GRID-UMOSFET WITH ELECTRIC FIELD SHIELDING OF GATE OXIDE

• US 20090072241A1
• Filed: 09/14/2007
• Published: 03/19/2009
• Est. Priority Date: 09/14/2007
• Status: Active Grant

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Svederg, Jan-Olov, Harris, Christopher, Konstantinov, Andrei
• Granted Patent: US 8,421,148 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A trench metal oxide semiconductor field effect transistor or UMOSFET, includes a buried region that extends beneath the trench and beyond a corner of the trench. The buried region is tied to a source potential of the UMOSFET, and splits the potential realized across the structure. This effectively shields the electric field from the corners of the trench to reduce gate oxide stress, and resultantly improves device performance and reliability.

Claims

1. A semiconductor device comprising:

a substrate of a first conductivity type;

a drift layer of the first conductivity type over the substrate;

a channel layer of a second conductivity type on the drift layer, the second conductivity type opposite the first conductivity type;

a source layer of the first conductivity type on the channel layer;

a source contact extending on the source layer;

a trench extending through the source layer and the channel layer, and into the drift layer, so that a bottom of the trench is within the drift layer;

a gate insulating layer on the sidewalls and the bottom of the trench;

a gate within the trench on the gate insulating layer;

a buried region of the second conductivity type within the drift layer, the buried region extending laterally underneath the trench and beyond a corner of the trench, so that a shallow region of the drift layer is between the bottom of the trench and the buried region; and

a conductive via through the source layer, the channel layer and the drift layer, electrically connecting the source contact to the buried region.

2. The semiconductor device of claim 1, wherein the drift, channel and source layers are silicon carbide epitaxial layers.

3. The semiconductor device of claim 1, wherein the conductive via is the second conductivity type and the source contact is embedded into an upper surface of the conductive via, and wherein the source contact embedded within the conductive via is surrounded by material of the second conductivity type and thereby separated from the source and drift layers of the first conductivity type.

4. The semiconductor device of claim 3, wherein the source contact is a metal.

5. The semiconductor device of claim 1, wherein the first conductivity type is n-type conductivity and the second conductivity type is p-type conductivity.

6. The semiconductor device of claim 1, comprising a plurality of additional conductive vias through the source layer, the channel layer and the drift layer, the plurality of additional conductive vias separated from each other and each electrically connecting the source contact to the buried region.

7. The semiconductor device of claim 1, wherein the buried region is an implanted region.

8. The semiconductor device of claim 1, wherein the gate is polysilicon.

16. The grid UMOSFET of claim 8, wherein the gates are polysilicon.

9. A grid UMOSFET comprising:

a substrate of a first conductivity type;

a drift layer of the first conductivity type over the substrate;

a channel layer of a second conductivity type on the drift layer, the second conductivity type opposite the first conductivity type;

a source layer of the first conductivity type on the channel layer;

a source contact having a plurality of source contact fingers extending on the source layer substantially parallel with respect to each other;

a plurality of trenches extending substantially parallel with respect to the source contact fingers, and through the source layer and the channel layer, into the drift layer, so that bottoms of the trenches are within the drift layer;

gate insulating layers on sidewalls and the bottoms of the trenches;

a plurality of gates respectively within the trenches on the gate insulating layers;

a plurality of buried regions of the second conductivity type within the drift layer, the buried regions respectively extending laterally underneath the trenches and beyond corners of the trenches, so that shallow regions of the drift layer are between the bottoms of the trenches and the buried regions; and

conductive vias through the source layer, the channel layer and the drift layer, electrically connecting the source contact fingers to the buried regions.

10. The grid UMOSFET of claim 9, wherein the drift, channel and source layers are silicon carbide epitaxial layers.

11. The grid UMOSFET of claim 9, wherein the conductive vias are the second conductivity type and the source contact fingers are embedded into an upper surface of respective ones of the conductive vias, and wherein the source contact fingers embedded within the conductive vias are surrounded by material of the second conductivity type and thereby separated from the source and drift layers by portions of the conductive vias.

12. The grid UMOSFET of claim 11, wherein the source contact is a metal.

13. The grid UMOSFET of claim 9, wherein the first conductivity type is n-type conductivity and the second conductivity type is p-type conductivity.

14. The grid UMOSFET of claim 9, wherein the source contact fingers are each respectively electrically connected to the buried regions by a plurality of the conductive vias.

15. The grid UMOSFET of claim 9, wherein the buried regions are implanted regions.

17. A semiconductor device comprising:

a substrate;

a plurality of semiconductor layers over the substrate, the semiconductor layers including a drift layer, a channel layer on the drift layer, and a source layer on the channel layer;

a trench MOSFET disposed within the semiconductor layers; and

a long channel JFET including a buried region within the drift layer, the buried region extending laterally underneath the trench MOSFET and beyond a peripheral side edge of the trench MOSFET, so that a shallow region of the drift layer is between the trench MOSFET and the buried region,

the buried region of the long channel JFET is electrically coupled to a source potential applied to the source layer of the trench MOSFET.

18. The semiconductor device of claim 17, wherein the semiconductor layers are silicon carbide epitaxial layers.

19. The semiconductor device of claim 17, wherein the drift layer and the source layer have n-type conductivity, and the buried region and the channel layer have p-type conductivity.

20. The semiconductor device of claim 17, further comprising:

a conductive via extending through the source layer and the channel layer, and into the drift layer; and

a source contact embedded within the conductive via and surrounded by material of the second conductivity type, to be separated from the source and drift layers by portions of the conductive via.