GRID-UMOSFET WITH ELECTRIC FIELD SHIELDING OF GATE OXIDE
First Claim
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1. A semiconductor device comprising:
- a substrate of a first conductivity type;
a drift layer of the first conductivity type over the substrate;
a channel layer of a second conductivity type on the drift layer, the second conductivity type opposite the first conductivity type;
a source layer of the first conductivity type on the channel layer;
a source contact extending on the source layer;
a trench extending through the source layer and the channel layer, and into the drift layer, so that a bottom of the trench is within the drift layer;
a gate insulating layer on the sidewalls and the bottom of the trench;
a gate within the trench on the gate insulating layer;
a buried region of the second conductivity type within the drift layer, the buried region extending laterally underneath the trench and beyond a corner of the trench, so that a shallow region of the drift layer is between the bottom of the trench and the buried region; and
a conductive via through the source layer, the channel layer and the drift layer, electrically connecting the source contact to the buried region.
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Abstract
A trench metal oxide semiconductor field effect transistor or UMOSFET, includes a buried region that extends beneath the trench and beyond a corner of the trench. The buried region is tied to a source potential of the UMOSFET, and splits the potential realized across the structure. This effectively shields the electric field from the corners of the trench to reduce gate oxide stress, and resultantly improves device performance and reliability.
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Citations
20 Claims
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1. A semiconductor device comprising:
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a substrate of a first conductivity type; a drift layer of the first conductivity type over the substrate; a channel layer of a second conductivity type on the drift layer, the second conductivity type opposite the first conductivity type; a source layer of the first conductivity type on the channel layer; a source contact extending on the source layer; a trench extending through the source layer and the channel layer, and into the drift layer, so that a bottom of the trench is within the drift layer; a gate insulating layer on the sidewalls and the bottom of the trench; a gate within the trench on the gate insulating layer; a buried region of the second conductivity type within the drift layer, the buried region extending laterally underneath the trench and beyond a corner of the trench, so that a shallow region of the drift layer is between the bottom of the trench and the buried region; and a conductive via through the source layer, the channel layer and the drift layer, electrically connecting the source contact to the buried region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 16)
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9. A grid UMOSFET comprising:
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a substrate of a first conductivity type; a drift layer of the first conductivity type over the substrate; a channel layer of a second conductivity type on the drift layer, the second conductivity type opposite the first conductivity type; a source layer of the first conductivity type on the channel layer; a source contact having a plurality of source contact fingers extending on the source layer substantially parallel with respect to each other; a plurality of trenches extending substantially parallel with respect to the source contact fingers, and through the source layer and the channel layer, into the drift layer, so that bottoms of the trenches are within the drift layer; gate insulating layers on sidewalls and the bottoms of the trenches; a plurality of gates respectively within the trenches on the gate insulating layers; a plurality of buried regions of the second conductivity type within the drift layer, the buried regions respectively extending laterally underneath the trenches and beyond corners of the trenches, so that shallow regions of the drift layer are between the bottoms of the trenches and the buried regions; and conductive vias through the source layer, the channel layer and the drift layer, electrically connecting the source contact fingers to the buried regions. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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17. A semiconductor device comprising:
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a substrate; a plurality of semiconductor layers over the substrate, the semiconductor layers including a drift layer, a channel layer on the drift layer, and a source layer on the channel layer; a trench MOSFET disposed within the semiconductor layers; and a long channel JFET including a buried region within the drift layer, the buried region extending laterally underneath the trench MOSFET and beyond a peripheral side edge of the trench MOSFET, so that a shallow region of the drift layer is between the trench MOSFET and the buried region, the buried region of the long channel JFET is electrically coupled to a source potential applied to the source layer of the trench MOSFET. - View Dependent Claims (18, 19, 20)
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Specification