Insulated Gate Bipolar Conduction Transistors (IBCTS) and Related Methods of Fabrication

• US 20090072242A1
• Filed: 09/18/2007
• Published: 03/19/2009
• Est. Priority Date: 09/18/2007
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Zhang, Qingchun
• Granted Patent: US 7,687,825 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT

Abstract

Insulated gate bipolar conduction transistors (IBCTs) are provided. The IBCT includes a drift layer having a first conductivity type. An emitter well region is provided in the drift layer and has a second conductivity type opposite the first conductivity type. A well region is provided in the drift layer and has the second conductivity type. The well region is spaced apart from the emitter well region. A space between the emitter well region and the well region defines a JFET region of the IBCT. An emitter region is provided in the well region and has the first conductivity type and a buried channel layer is provided on the emitter well region, the well region and the JFET region and has the first conductivity type. Related methods of fabrication are also provided.

Claims

1. An insulated gate bipolar conduction transistor (IBCT), comprising:

a drift layer having a first conductivity type;

an emitter well region in the drift layer and having a second conductivity type opposite the first conductivity type;

a well region in the drift layer and having the second conductivity type, wherein the well region is spaced apart from the emitter well region and wherein a space between the emitter well region and the well region defines a JFET region of the IBCT;

an emitter region in the well region and having the first conductivity type; and

a buried channel layer on the emitter well region, the well region and the JFET region and having the first conductivity type.

2. The IBCT of claim 1, wherein the buried channel layer comprises an epitaxial layer.

3. The IBCT of claim 2, wherein the buried channel layer has a thickness of from about 1000 to about 3000 Å

.

4. The IBCT of claim 2, wherein the buried channel layer has a doping concentration of from about 5×

10¹⁵ to about 1×

10¹⁷ cm<sup>−

3</sup>.

5. The IBCT of claim 2, further comprising a substrate having the second conductivity type,

wherein the drift layer is provided in the substrate;

wherein the substrate comprises an off-axis n-type silicon carbide substrate; and

wherein the drift layer and the buried channel layer comprise p-type silicon carbide epitaxial layers.

6. The IBCT of claim 1, wherein the drift layer has a doping concentration of from about 2×

10¹⁴ cm<sup>−

3</sup> to about 6×

10¹⁴ cm<sup>−

3</sup> and a thickness of from about 100 μ

m to about 120 μ

m for greater than 10 kV applications.

7. The IBCT of claim 1, wherein the IBCT has a blocking voltage of about 8.0 kV and a leakage current of less than about 0.1 mA/cm².

8. The IBCT of claim 1, wherein the IBCT has a differential on-resistance of 50 mΩ

·

cm² at a gate bias of −

16V at 25°

C.

9. The IBCT of claim 1, wherein the first conductivity type comprises n-type and the second conductivity type comprises p-type.

10. The IBCT of claim 1, wherein the first conductivity type comprises p-type and the second conductivity type comprises n-type.

11. The IBCT of claim 1, further comprising:

a substrate having the second conductivity type, wherein the drift layer is provided in the substrate; and

a buffer layer between the substrate and the drift layer, wherein the buffer layer has the first conductivity type.

12. An insulated gate bipolar conduction transistor (IBCT) comprising a bipolar junction transistor (BJT) portion and an insulated gate bipolar transistor (IGBT) portion.

13. A method of forming an insulated gate bipolar conduction transistor (IBCT), comprising:

forming a drift layer having a first conductivity type;

forming an emitter well region in the drift layer and having a second conductivity type opposite the first conductivity type;

forming a well region in the drift layer and having the second conductivity type, wherein the well region is spaced apart from the emitter well region and wherein a space between the emitter well region and the well region defines a JFET region of the IBCT;

forming an emitter region in the well region and having the first conductivity type; and

forming a buried channel layer on the emitter well region, the well region and the JFET region and having the first conductivity type.

14. The method of claim 13:

wherein forming the emitter well region comprises forming the emitter well region using epitaxial growth; and

wherein forming the well region comprises forming the well region using epitaxial growth.

15. The method of claim 13, wherein forming the buried channel layer comprises forming the buried channel layer using epitaxial regrowth with a same polarity as the drift layer.

16. The method of claim 15, wherein forming the buried channel layer comprises forming a buried channel layer having a thickness of from about 1000 to about 3000 Å

.

17. The method of claim 15, wherein forming the buried channel layer comprises forming the buried channel layer having a doping concentration of from about 5×

10¹⁵ about 1×

10¹⁷ cm<sup>−

3</sup>.

18. The method of claim 13, further comprising providing an off-axis n-type silicon carbide substrate,

wherein forming the drift layer comprises forming a p-type silicon carbide epitaxial drift layer;

and

wherein forming the buried channel layer comprises forming a p-type silicon carbide epitaxial channel layer.

19. The method of claim 13, wherein forming the drift layer comprises forming the drift layer having a doping concentration of from about 2×

10¹⁴ cm<sup>−

3</sup> to about 6×

10¹⁴ cm<sup>−

3</sup> and a thickness of from about 100 μ

m to about 120 μ

m.

20. The method of claim 13, wherein the IBCT has a blocking voltage of about 8.0 kV and a leakage current of less than about 0.1 mA/cm².

21. The method of claim 13, wherein the IBCT has a differential on-resistance of 50 mΩ

·

cm² at a gate bias of −

16V at 25°

C.

22. The method of claim 13, wherein the first conductivity type comprises n-type and the second conductivity type comprises p-type.

23. The method of claim 13, wherein the first conductivity type comprises p-type and the second conductivity type comprises n-type.

24. The method of claim 13, further comprising:

providing a substrate, wherein forming the drift layer comprises forming the drift layer in the substrate; and

forming a buffer layer between the substrate and the drift layer, wherein the buffer layer has the first conductivity type.

25. A silicon carbide insulated gate bipolar conduction transistor (IBCT), comprising:

an n-type conductivity silicon carbide substrate;

a p-type silicon carbide drift layer on the silicon carbide substrate;

an n-type silicon carbide emitter well region in the p-type silicon carbide drift layer;

an n-type silicon carbide well region in the p-type silicon carbide drift layer, wherein the n-type silicon carbide well region is spaced apart from the n-type silicon carbide emitter well region and wherein a space between the n-type silicon carbide emitter well region and the n-type silicon carbide well region defines a JFET region of the IBCT;

a p-type silicon carbide emitter region in the well region; and

a p-type silicon carbide buried channel layer on the emitter well region, the well region and the JFET region.