Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact

• US 20090072301A1
• Filed: 11/18/2008
• Published: 03/19/2009
• Est. Priority Date: 02/11/2005
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Lui, Sik K., Bhalla, Anup
• Granted Patent: US 7,745,878 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one active cell further includes a trenched source contact opened between the trenches wherein the trenched source contact opened through a source region into a body region for electrically connecting the source region to a source metal disposed on top of an insulation layer wherein a trench bottom surface of the trenched source contact further covered with a conductive material to function as an integrated Schottky barrier diode in said active cell. A shielding structure is disposed at the bottom and insulated from the trenched gate to provide shielding effect for both the trenched gate and the Schottky diode.

Claims

1. A semiconductor power device comprising a plurality of power transistor cells surrounded by a continuously extended trench opened in a semiconductor substrate wherein:

at least one of said cells constituting an active cell having a source region disposed next to a trenched gate disposed in said extended trench surrounding said cell and electrically connecting to a gate pad wherein said trenched gate further having a bottom shielding electrode filled with a gate material disposed below and insulated from said trenched gate wherein said bottom shielding electrode filled with said gate material having a tapered profile toward a bottom of said trench with a lining layer surrounded said gate material having a correspondingly gradually increased thickness; and

at least an active cell further includes a trenched source contact opened between said trenches wherein said trenched source contact opened through a source region into a body region for electrically connecting the source region to a source metal disposed on top of an insulation layer wherein a trench bottom surface of said trenched source contact further covered with a conductive material to function as an integrated Schottky barrier diode in said active cell.

2. The semiconductor power device of claim 1 wherein:

at least one of said cells constituting a connecting cell surrounded by said trench with a portion functioning as a connecting trench filled with said gate material for electrically connecting between said bottom shielding electrode and a metal disposed directly on top of said connecting trench.

3. The semiconductor power device of claim 1 wherein:

an insulator layer is disposed above said bottom shielding electrode to insulate said shielding electrode from said trenched gate wherein said insulator layer above said bottom shielding electrode is disposed in said trench with a predefined depth controlled by a timed etch process.

4. The semiconductor power device of claim 1 wherein:

said bottom shielding electrode filled with said gate material having a stepwise tapered profile toward a bottom of said trench with a lining layer surrounded said gate material having a correspondingly stepwise increased thickness.

5. The semiconductor power device of claim 1 wherein:

said power transistor cells further comprising trenched metal oxide semiconductor field effect transistor (MOSFET) cells.

6. The semiconductor power device of claim 1 wherein:

said trenched source contact is disposed in a dedicated area on said semiconductor power device for connecting said trenched source contact to a separate contact pad near said dedicated area.

7. A semiconductor power device comprising a plurality of power transistor cells surrounded by a continuously extended trench opened in a semiconductor substrate wherein:

at least one of said cells constituting an active cell having a source region disposed next to a trenched gate disposed in said extended trench surrounding said cell and electrically connecting to a gate pad;

a gate-to-drain shielding region formed as a body dopant region disposed below said trenched gate; and

at least an active cell further includes a trenched source contact disposed substantially at a central portion of said active cell wherein said trenched source contact opened into a source region and extended into a body region of said active cell for electrically connecting the source region to a source metal disposed on top of an insulation layer wherein a trench bottom surface of said trenched source contact further covered with a conductive material to function as an integrated Schottky barrier diode in said active cell.

8. The trenched power semiconductor power device of claim 7 wherein:

said conductive material covering said trench bottom surface of said source contact trench includes a low barrier height metal.

9. The trenched power semiconductor power device of claim 7 wherein:

said conductive material covering said trench bottom surface of said source contact trench includes a Ti/TiN or TiSi₂/TiNmaterial.

10. The trenched power semiconductor power device of claim 7 further comprising:

a punch through prevention region doped with a body dopant disposed below said source region along trench walls of said source contact trench.

11. The semiconductor power device of claim 7 wherein:

said power transistor cells further comprising trenched metal oxide semiconductor field effect transistor (MOSFET) cells.

12. A semiconductor power device comprising a plurality of power transistor cells surrounded by a continuously extended trench opened in a semiconductor substrate wherein:

at least one of said cells constituting an active cell having a source region disposed next to a trenched gate disposed in said extended trench surrounding said cell and electrically connecting to a gate pad;

a thick oxide layer disposed at the bottom portion below said trenched gate and a body dopant region surrounding a bottom and a lower portions of sidewalls around said thick oxide layer filling the bottom portion in the trench below the trenched gates; and

at least an active cell further includes a trenched source contact disposed substantially at a central portion of said active cell wherein said trenched source contact opened into a source region and extended into a body region of said active cell for electrically connecting the source region to a source metal disposed on top of an insulation layer wherein a trench bottom surface of said trenched source contact further covered with a conductive material to function as an integrated Schottky barrier diode in said active cell.

13. The trenched power semiconductor power device of claim 12 wherein:

said conductive material covering said trench bottom surface of said source contact trench includes a low barrier height metal.

14. The trenched power semiconductor power device of claim 12 wherein:

said conductive material covering said trench bottom surface of said source contact trench includes a Ti/TiN or TiSi₂/TiNmaterial.

15. The trenched power semiconductor power device of claim 12 further comprising:

a punch through prevention region doped with a body dopant disposed below said source region along trench walls of said source contact trench.

16. The semiconductor power device of claim 12 wherein:

said power transistor cells further comprising trenched metal oxide semiconductor field effect transistor (MOSFET) cells.

17. The semiconductor power device of claim 12 wherein:

said semiconductor power device having a reduced gate to drain capacitance Cgd depending on a depth of said oxide layer below the trenched gate.

18. A method for manufacturing a semiconductor power device comprising:

opening a trench in a substrate for surrounding a plurality of power transistor cells and filling said trench with a gate material; and

applying a time etch for etching back said gate material from a selected portion of said trench followed by covering a bottom portion of said gate material in said selected portion of said trench with a shielding insulation to form a bottom shielding electrode while keeping said gate material in a remainder portion of said trench to maintain direct electric connection to said shielding trench bottom;

filling said selected portion of said trench with said gate material to form a trenched gate; and

forming an insulation layer for covering a top surface of said semiconductor power device and opening a plurality of source contact trenches extending down to a body region between trenched gate and depositing a conductive material over a bottom surface of said source contact trench to function as an integrated Schottky barrier diode in said semiconductor power device.

19. The method of claim 18 further comprising:

controlling said time etch in removing said gate material from a top portion of said selected portion of said trench for controlling a depth of a trenched gate of said semiconductor power device.

20. A semiconductor power device comprising:

a plurality of insulated trenched gate surrounded by a source region doped with a first conductivity type dopant deposited on an upper surface of a body region doped with a second conductivity type dopant opposite to said first conductivity type;

a trenched source contact opened between said trenched gates wherein said trenched source contact opened through said source region into said body region for electrically connecting the source region to a source metal disposed on top of an insulation layer wherein a trench bottom surface of said trenched source contact further covered with a low barrier height metal to function as an integrated Schottky barrier diode in said active cell.

21. The semiconductor power device of claim 20 wherein:

said low barrier height material consists of Ti/TiN or TiSi₂/TiN.

22. The semiconductor power device of claim 20 further comprising:

a shielding structure under said trench gate.

23. The semiconductor power device of claim 22 wherein:

said shielding structure is a bottom shielding electrode deposited below and insulated from said trenched gate.

24. The semiconductor power device of claim 23 wherein:

bottom shielding electrode is connected to source voltage.

25. The semiconductor power device of claim 23 wherein:

said bottom shielding electrode is connected to a bottom gate pad.

26. The semiconductor power device of claim 23 wherein:

said bottom shielding electrode is floating.

27. The semiconductor power device of claim 22 wherein:

said shielding structure consists of a body dopant region disposed at the bottom and insulated from said trenched gate.

28. The semiconductor power device of claim 22 wherein:

said shielding structure consists of a thick oxide layer disposed at the bottom portion below said trenched gate and a body dopant region surrounding a bottom and a lower portion of sidewalls around said thick oxide layer filling the bottom portion in the trench below the trenched gates

29. The semiconductor power device of claim 20 wherein:

said shielding structure extends to a depth that is deeper than said trench bottom surface of said trenched source contact.

30. A semiconductor power device comprising:

a plurality of insulated trenched gate surrounded by a source region doped with a first conductivity type dopant deposited on an upper surface of a body region doped with a second conductivity type dopant opposite to said first conductivity type;

a trenched source contact opened between said trenched gates wherein said trenched source contact opened through said source region into said body region for electrically connecting the source region to a source metal disposed on top of an insulation layer wherein a trench bottom surface of said trenched source contact further covered with a conductive material to function as an integrated Schottky barrier diode in said active cell; and

a shielding structure disposed at the bottom and insulated from said trenched gate.

31. The semiconductor power device of claim 30 wherein said conductive material is a low barrier height metal.

32. The semiconductor power device of claim 30 wherein:

said low barrier height material consists of Ti/TiN or TiSi₂/TiN.

33. The semiconductor power device of claim 30 wherein:

said shielding structure extends to a depth that is deeper than said trench bottom surface of said trenched source contact.

34. The semiconductor power device of claim 30 wherein:

said shielding structure is a bottom shielding electrode deposited below and insulated from said trenched gate.

35. The semiconductor power device of claim 34 wherein:

said bottom shielding electrode is connected to source voltage.

36. The semiconductor power device of claim 34 wherein:

said bottom shielding electrode is connected to a bottom gate pad.

37. The semiconductor power device of claim 34 wherein:

said bottom shielding electrode is floating.

38. The semiconductor power device of claim 30 wherein:

said shielding structure consists of a body dopant region disposed at the bottom and insulated from said trenched gate.

39. The semiconductor power device of claim 30 wherein:

said shielding structure consists of a thick oxide layer disposed at the bottom portion below said trenched gate and a body dopant region surrounding a bottom and a lower portions of sidewalls around said thick oxide layer filling the bottom portion in the trench below the trenched gates.