HARDENED TRANSISTORS IN SOI DEVICES

• US 20090072313A1
• Filed: 09/19/2007
• Published: 03/19/2009
• Est. Priority Date: 09/19/2007
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Oldiges, Philip J., Cai, Jin, Ning, Tak H., Shahidi, Ghavam G., Haensch, Wilfried E.
• Application Number:
  US11/857,569
• Publication Number:
  US 20090072313A1
• Time in Patent Office: Days
• US Class Current: 257/351
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/07 the components having an active region in common
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect

Abstract

A series transistor device includes a series source, a series drain, a first constituent transistor, and a second constituent transistor. The first constituent transistor has a first source and a first drain, and the second constituent transistor has a second source and a second drain. All of the constituent transistors have a same conductivity type. The series source is the first source, and the series drain is the second drain. A drain of one of the constituent transistors is merged with a source of another of the constituent transistors.

Claims

1. A series transistor device, comprising:

a series source;

a series drain;

a first constituent transistor having a first source and a first drain; and

a second constituent transistor having a second source and a second drain, wherein

all of the constituent transistors have a same conductivity type,

the series source is the first source,

the series drain is the second drain, and

a drain of one of the constituent transistors is merged with a source of another of the constituent transistors.

2. The device of claim 1, wherein the series transistor device is a SOI device.

3. The device of claim 1, wherein the first drain is merged with the second source.

4. The device of claim 1, further comprising a third constituent transistor electrically positioned between the first constituent transistor and the second constituent transistor.

5. The device of claim 1, wherein at least two of the constituent transistors have separate gates that are directly electrically connected to one another.

6. The device of claim 1, wherein at least two of the constituent transistors have a shared common gate.

7. The device of claim 1, wherein at least two of the constituent transistors have substantially different channel lengths than one another.

8. The device of claim 1, wherein at least two of the constituent transistors have substantially different characteristics than one another.

9. The device of claim 1, wherein at least two of the constituent transistors have substantially identical characteristics.

10. The device of claim 1, wherein the device bodies of all the constituent transistors are electrically isolated from one another.

11. A series transistor device, comprising:

a series source;

a series drain;

a first constituent transistor having a first source and a first drain; and

a second constituent transistor having a second source and a second drain, wherein

all of the constituent transistors have a same conductivity type,

the series source is the first source,

the series drain is the second drain, and

at least two of the transistors have substantially different characteristics than one another.

12. The device of claim 11, wherein at least two of the constituent transistors have substantially different channel lengths than one another.

13. An inverter circuit, comprising:

a n-channel transistor device; and

a p-channel transistor device, wherein

an input is directly electrically connected to a gate of the n-channel transistor device and a gate of the p-channel transistor device, and

at least one of the n-channel transistor device and the p-channel transistor device is a series transistor device.

14. The inverter circuit of claim 13, wherein the at least one series transistor device includes:

a series source;

a series drain;

a first constituent transistor having a first source and a first drain; and

a second constituent transistor having a second source and a second drain, wherein

all of the constituent transistors have a same conductivity type,

the series source is the first source,

the series drain is the second drain.

15. The inverter circuit of claim 14, wherein a drain of one of the constituent transistors is merged with a source of another of the constituent transistors.

16. The inverter circuit of claim 14, wherein at least two of the constituent transistors have substantially different characteristics than one another.

17. The inverter circuit of claim 14, wherein at least two of the constituent transistors have a shared common gate.

18. The inverter circuit of claim 13, wherein the p-channel transistor device is the series transistor device.

19. The inverter circuit of claim 13, wherein the n-channel transistor device is the series transistor device.

20. The inverter circuit of claim 13, wherein both the n-channel transistor device and the p-channel transistor device are series SOI transistor devices.