DUAL SHALLOW TRENCH ISOLATION STRUCTURE
First Claim
1. A method of manufacturing a semiconductor structure, comprising:
- forming a trench having a first depth and containing a pair of substantially planar trench sidewalls in a semiconductor substrate;
forming an oxidation barrier layer on a lower portion of said pair of substantially planar trench sidewalls;
forming a thermal oxide collar on an upper portion of said pair of substantially planar trench sidewalls above a second depth, wherein said pair of substantially planar trench sidewalls becomes separated by an upper portion width within said upper portion; and
etching said lower portion of said pair of substantially planar trench sidewalls below said second depth to form another pair of substantially planar trench sidewalls separated by a lower portion width, wherein said lower portion width is greater than said upper portion width.
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Accused Products
Abstract
A protective dielectric layer is formed on a first shallow trench having straight sidewalls, while exposing a second shallow trench. An oxidation barrier layer is formed on the semiconductor substrate. A resist is applied and recessed within the second shallow trench. The oxidation barrier layer is removed above the recessed resist. The resist is removed and thermal oxidation is performed so that a thermal oxide collar is formed above the remaining oxidation mask layer. The oxidation barrier layer is thereafter removed and exposed semiconductor area therebelow depth is etched to form a bottle shaped shallow trench. The first and the bottle shaped trenches are filled with a dielectric material to form a straight sidewall shallow trench isolation structure and a bottle shallow trench isolation structure, respectively. Both shallow trench isolation structures may be employed to provide optimal electrical isolation and device performance to semiconductor devices having different depths.
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Citations
20 Claims
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1. A method of manufacturing a semiconductor structure, comprising:
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forming a trench having a first depth and containing a pair of substantially planar trench sidewalls in a semiconductor substrate; forming an oxidation barrier layer on a lower portion of said pair of substantially planar trench sidewalls; forming a thermal oxide collar on an upper portion of said pair of substantially planar trench sidewalls above a second depth, wherein said pair of substantially planar trench sidewalls becomes separated by an upper portion width within said upper portion; and etching said lower portion of said pair of substantially planar trench sidewalls below said second depth to form another pair of substantially planar trench sidewalls separated by a lower portion width, wherein said lower portion width is greater than said upper portion width. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor structure comprising:
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a first shallow trench isolation (STI) structure comprising a dielectric material, located in a semiconductor substrate, and containing a first pair of substantially planar STI sidewalls separated by a first width and a first STI bottom surface located at a first depth, wherein said first pair of substantially planar STI sidewalls extends from a top surface of said semiconductor substrate to said first STI bottom surface; and a second shallow trench isolation (STI) structure comprising said dielectric material and located in said semiconductor substrate and having an upper portion and a lower portion, wherein said upper portion contains a second pair of substantially planar STI sidewalls separated by a second width and extending from said top surface to a second depth, and wherein said lower portion contains a third pair of substantially planar STI sidewalls separated by a third width and extending from said second depth to a third depth and adjoining a second STI bottom surface at said third depth, and wherein said third width is greater than said second width. - View Dependent Claims (13, 14, 15, 16)
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17. A semiconductor structure comprising:
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a first trench located in a semiconductor substrate and containing a first pair of substantially planar trench sidewalls separated by a first width and a first trench bottom surface located at a first depth, wherein said first pair of substantially planar trench sidewalls extends from a top surface of said semiconductor substrate to said first trench bottom surface; and a second trench located in said semiconductor substrate and having an upper portion and a lower portion, wherein said upper portion contains a second pair of substantially planar trench sidewalls separated by a second width and extending from said top surface to a second depth, and wherein said lower portion contains a third pair of substantially planar trench sidewalls separated by a third width and extending from said second depth to a third depth and adjoining a second trench bottom surface at said third depth, and wherein said third width is greater than said second width. - View Dependent Claims (18, 19, 20)
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Specification