DUAL SHALLOW TRENCH ISOLATION STRUCTURE

• US 20090072355A1
• Filed: 09/17/2007
• Published: 03/19/2009
• Est. Priority Date: 09/17/2007
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Faltermeier, Johnathan E., Edge, Lisa F., Cheng, Kangguo, Kusaba, Naoyoshi
• Application Number:
  US11/856,260
• Publication Number:
  US 20090072355A1
• Time in Patent Office: Days
• US Class Current: 257/622
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence

Abstract

A protective dielectric layer is formed on a first shallow trench having straight sidewalls, while exposing a second shallow trench. An oxidation barrier layer is formed on the semiconductor substrate. A resist is applied and recessed within the second shallow trench. The oxidation barrier layer is removed above the recessed resist. The resist is removed and thermal oxidation is performed so that a thermal oxide collar is formed above the remaining oxidation mask layer. The oxidation barrier layer is thereafter removed and exposed semiconductor area therebelow depth is etched to form a bottle shaped shallow trench. The first and the bottle shaped trenches are filled with a dielectric material to form a straight sidewall shallow trench isolation structure and a bottle shallow trench isolation structure, respectively. Both shallow trench isolation structures may be employed to provide optimal electrical isolation and device performance to semiconductor devices having different depths.

Claims

1. A method of manufacturing a semiconductor structure, comprising:

forming a trench having a first depth and containing a pair of substantially planar trench sidewalls in a semiconductor substrate;

forming an oxidation barrier layer on a lower portion of said pair of substantially planar trench sidewalls;

forming a thermal oxide collar on an upper portion of said pair of substantially planar trench sidewalls above a second depth, wherein said pair of substantially planar trench sidewalls becomes separated by an upper portion width within said upper portion; and

etching said lower portion of said pair of substantially planar trench sidewalls below said second depth to form another pair of substantially planar trench sidewalls separated by a lower portion width, wherein said lower portion width is greater than said upper portion width.

2. The method of claim 1, further comprising removing said oxidation barrier layer from said lower portion of said pair of substantially planar trench sidewalls after said forming of said thermal oxide collar and prior to said etching of said lower portion of said pair of substantially planar trench sidewalls.

3. The method of claim 2, wherein said forming of said oxidation barrier layer on said lower portion of said pair of substantially planar trench sidewalls comprises:

forming said oxidation barrier layer on the entirety of said pair of substantially planar trench sidewalls within said trench; and

removing a portion of said oxidation barrier layer on said upper portion of said pair of substantially planar trench sidewalls.

4. The method of claim 3, further comprising:

filling said trench with a resist after said forming of said oxidation barrier layer on said entirety of said pair of substantially planar trench sidewalls; and

recessing said resist down to said second depth.

5. The method of claim 1, further comprising forming a dielectric pad layer directly on a top surface of said semiconductor substrate prior to said forming of said trench, wherein said dielectric pad layer is resistant to thermal oxidation.

6. The method of claim 5, wherein said semiconductor substrate comprises silicon, said thermal oxide collar comprises silicon oxide, and said oxidation barrier layer comprises silicon nitride, and said dielectric pad layer comprises silicon nitride.

7. The method of claim 1, wherein said etching of said lower portion is substantially isotropic, wherein said etching of said lower portion forms a trench bottom wall at a third depth, and wherein said lower portion width less said upper portion width is substantially the same as twice said third depth less said first depth.

8. The method of claim 1, further comprising:

forming another trench having said first depth and containing a third pair of substantially planar trench sidewalls in said semiconductor substrate at the same step as said forming of said trench; and

forming a protective dielectric layer within said another trench prior to said forming of said oxidation mask layer.

9. The method of claim 8, further comprising:

forming said protective dielectric layer within said trench; and

removing said protective dielectric layer within said trench from within said trench prior to said forming of said oxidation mask layer.

10. The method of claim 9, further comprising:

filling said trench and said another trench with a dielectric material;

planarizing said dielectric material employing a dielectric pad layer as a stopping layer; and

recessing said dielectric material to a height that is substantially flush with a top surface of said semiconductor substrate.

11. The method of claim 1, wherein said protective dielectric layer and said thermal oxide collar comprise silicon oxide, and protective dielectric layer and said thermal oxide collar are removed at a same etch step.

12. A semiconductor structure comprising:

a first shallow trench isolation (STI) structure comprising a dielectric material, located in a semiconductor substrate, and containing a first pair of substantially planar STI sidewalls separated by a first width and a first STI bottom surface located at a first depth, wherein said first pair of substantially planar STI sidewalls extends from a top surface of said semiconductor substrate to said first STI bottom surface; and

a second shallow trench isolation (STI) structure comprising said dielectric material and located in said semiconductor substrate and having an upper portion and a lower portion, wherein said upper portion contains a second pair of substantially planar STI sidewalls separated by a second width and extending from said top surface to a second depth, and wherein said lower portion contains a third pair of substantially planar STI sidewalls separated by a third width and extending from said second depth to a third depth and adjoining a second STI bottom surface at said third depth, and wherein said third width is greater than said second width.

13. The semiconductor structure of claim 12, wherein said third depth is greater than said first depth, and wherein said second depth is less than said first depth.

14. The semiconductor structure of claim 12, wherein said third width less said second width is less than twice said third depth less said first depth.

15. The semiconductor structure of claim 12, wherein said first STI bottom surface and said second STI bottom surface are substantially horizontal and planar.

16. The semiconductor structure of claim 12, further comprising:

at least one semiconductor device abutting said first pair of substantially planar STI sidewalls and extending from said top surface to a depth below said second depth; and

at least another semiconductor device abutting said second pair of substantially planar STI sidewalls and located above said second depth.

17. A semiconductor structure comprising:

a first trench located in a semiconductor substrate and containing a first pair of substantially planar trench sidewalls separated by a first width and a first trench bottom surface located at a first depth, wherein said first pair of substantially planar trench sidewalls extends from a top surface of said semiconductor substrate to said first trench bottom surface; and

a second trench located in said semiconductor substrate and having an upper portion and a lower portion, wherein said upper portion contains a second pair of substantially planar trench sidewalls separated by a second width and extending from said top surface to a second depth, and wherein said lower portion contains a third pair of substantially planar trench sidewalls separated by a third width and extending from said second depth to a third depth and adjoining a second trench bottom surface at said third depth, and wherein said third width is greater than said second width.

18. The semiconductor structure of claim 17, wherein said third depth is greater than said first depth, and wherein said second depth is less than said first depth.

19. The semiconductor structure of claim 17, wherein said third width less said second width is less than twice said third depth less said first depth.

20. The semiconductor structure of claim 17, wherein said first trench bottom surface and said second trench bottom surface are substantially horizontal and planar.