SEMICONDUCTOR DEVICE

• US 20090072379A1
• Filed: 09/14/2007
• Published: 03/19/2009
• Est. Priority Date: 09/14/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Mahler, Joachim, Hoeglauer, Josef, Mengel, Manfred, Engl, Reimund, Ewe, Henrik, Dangelmaier, Jochen
• Granted Patent: US 9,059,083 B2
• Time in Patent Office: Days
• US Class Current: 257/700
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/02288 printing, e.g. ink-jet printing per se B41J
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/31105 Etching inorganic layers
• CPC Class Codes: H01L 21/4821 Flat leads, e.g. lead frames with or without insulating supports
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/2402 Laminated, e.g. MCM-L type
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/24246 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/24998 Reinforcing structures, e.g. ramp-like support
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/76155 : Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/82001 : involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/82039 : using a laser
• CPC Class Codes: H01L 2224/82101 : by additive methods, e.g. direct writing
• CPC Class Codes: H01L 2224/82102 : using jetting, e.g. ink jet
• CPC Class Codes: H01L 2224/82103 : using laser direct writing
• CPC Class Codes: H01L 2224/82951 : Forming additional members
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/49524 : the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49534 : Multi-layer
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H05K 3/4661 : Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor other insulating materials H05K3/387

Abstract

A semiconductor device is disclosed. One embodiment includes a carrier, a semiconductor chip attached to the carrier, a first conducting line having a first thickness and being deposited over the semiconductor chip and the carrier and a second conducting line having a second thickness and being deposited over the semiconductor chip and the carrier. The first thickness is smaller than the second thickness.

Claims

1. A semiconductor device comprising:

a carrier;

a semiconductor chip attached to the carrier;

a first conducting line having a first thickness and being deposited over the semiconductor chip and the carrier;

a second conducting line having a second thickness and being deposited over the semiconductor chip and the carrier; and

wherein the first thickness is smaller than the second thickness.

2. The semiconductor device of claim 1, further comprising:

an insulating support layer on which the first conducting line is deposited.

3. The semiconductor device of claim 2, comprising wherein the second conducting line is deposited on the insulating support layer.

4. The semiconductor device of claim 1, further comprising:

an insulating barrier layer which covers the first conducting line and which leaves the second conducting line uncovered.

5. The semiconductor device of claim 4, further comprising:

a third conducting line deposited over the insulating barrier layer.

6. The semiconductor device of claim 1, comprising wherein the carrier is made of metal.

7. The semiconductor device of claim 1, comprising wherein the carrier is of a TSLP type.

8. The semiconductor device of claim 1, comprising wherein the carrier is made of an insulating material.

9. The semiconductor device of claim 1, further comprising:

a mold material encapsulating the semiconductor chip and the first and second conducting lines.

10. A method of manufacturing a semiconductor device, comprising:

providing a carrier;

attaching a semiconductor chip to the carrier;

depositing one or more conductive materials over the semiconductor chip and the carrier to form a first conducting line and a base part of a second conducting line;

applying an insulating barrier layer over the first conducting line, thereby leaving the base part of the second conducting line uncovered; and

depositing a conductive material over the uncovered base part of the second conducting line to form the second conducting line.

11. The method of claim 10, wherein the insulating barrier layer is applied in a structured manner.

12. The method of claim 11, comprising applying the insulating barrier layer by printing or dispensing a liquid polymer over the first conducting line.

13. The method of claim 10, comprising applying the insulating barrier layer by depositing an unstructured layer of insulating material and by structuring the unstructured layer of insulating material.

14. The method of claim 13, comprising applying the unstructured layer of insulating material by dispensing or spin-coating or spray-coating or lamination.

15. The method of claim 13, comprising structuring the unstructured layer of insulating material by lithographic processes or by laser ablation.

16. The method of claim 10, comprising depositing the one or more conductive materials over the semiconductor chip in a structured manner.

17. The method of claim 16, comprising depositing the one or more conductive materials to form the first conducting line and a base part of a second conducting line by printing.

18. The method of claim 16, wherein depositing the one or more conductive materials to form the first conducting line and a base part of a second conducting line comprises:

applying a structured seed layer; and

growing the conductive material on the structured seed layer.

19. The method of claim 18, comprising:

depositing the one or more conductive materials to form the first conducting line and a base part of a second conducting line by electroless plating; and

depositing the conductive material to form the second conducting line over the base part of the second conducting line by a galvanic process.

20. The method of claim 10, further comprising:

depositing a conductive material over the insulating barrier layer to form a third conducting line.

21. A semiconductor device comprising:

a carrier made of metal;

a semiconductor chip attached to the carrier;

a first conducting line deposited over the semiconductor chip and the carrier;

an insulating layer applied over the first conducting line; and

a second conducting line deposited over the insulating layer.

22. The semiconductor device of claim 21, comprising:

wherein the first conducting line and the second conducting line are crossing each other;

wherein the carrier is a TSLP type carrier;

a mold material encapsulating the semiconductor chip and the first and second conducting lines; and

an insulating support layer on which the first conducting line is deposited.

23. A method of manufacturing a semiconductor device, comprising:

providing a carrier;

attaching a semiconductor chip to the carrier;

depositing a first conducting line over the semiconductor chip and the carrier in a structured manner;

applying an insulating layer over the first conducting line; and

depositing a second conducting line over the insulating layer.

24. The method of claim 23, comprising depositing the second conducting line over the insulating layer in a structured manner;

wherein depositing the first conducting line comprises applying a structured seed layer, and growing conductive material on the structured seed layer to form the first conducting line; and

wherein depositing the second conducting line comprises applying a structured seed layer, and growing conductive material on the structured seed layer to form the second conducting line.

25. The method of claim 23, comprising:

depositing the first conducting line and the second conducting line by printing.