SEMICONDUCTOR DEVICE WITH INDUCTOR

• US 20090072388A1
• Filed: 09/17/2007
• Published: 03/19/2009
• Est. Priority Date: 09/17/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Tews, Helmut, Barth, Hans-Joachim, Jetten, Hans-Gerd
• Granted Patent: US 7,986,023 B2
• Time in Patent Office: Days
• US Class Current: 257/724
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 23/5388 for flat cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 Manganese [Mn]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01044 Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01059 : Praseodymium [Pr]
• CPC Class Codes: H01L 2924/01063 : Europium [Eu]
• CPC Class Codes: H01L 2924/01064 : Gadolinium [Gd]
• CPC Class Codes: H01L 2924/01066 : Dysprosium [Dy]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01105 : Rare earth metals
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

One or more embodiments are directed to a semiconductor structure, comprising: a support; a semiconductor chip at least partially embedded within the support; and an inductor electrically coupled to the chip, at least a portion of the inductor overlying the support outside the lateral boundary of the chip.

Claims

1. A semiconductor structure, comprising:

a support;

a semiconductor chip at least partially embedded within said support; and

an inductor electrically coupled to said chip, at least a portion of said inductor overlying said support outside the lateral boundary of said chip.

2. The structure of claim 1, wherein essentially all of said inductor overlies said support outside the lateral boundary of said chip.

3. The structure of claim 1, further comprising a magnetic region at least partially underlying or at least partially overlying said inductor.

4. The structure of claim 3, wherein said magnetic region at least partially underlies said inductor.

5. The structure of claim 3, wherein said magnetic region is at least partially embedded within said support, said magnetic region being laterally disposed from said chip.

6. The structure of claim 1, wherein said inductor is a loop inductor.

7. The structure of claim 1, wherein said inductor is a spiral inductor.

8. The structure of claim 1, wherein said inductor comprises a metallic material.

9. The structure of claim 3, wherein said magnetic region comprises a ferromagnetic material.

10. A semiconductor structure, comprising:

a support;

a semiconductor die at least partially embedded within said support; and

a magnetic region at least partially embedded within said support, said magnetic region laterally disposed from said chip.

11. The structure of claim 10, further comprising a conductive layer coupled to said chip, said conductive layer at least partially overlying said magnetic region.

12. The structure device of claim 11, wherein at least a portion of said conductive layer forms an inductor coil, at least a portion of said inductor coil overlying said magnetic region.

13. The structure of claim 10, wherein said magnetic region comprises a ferromagnetic material.

14. The structure of claim 11, wherein said conductive layer is a redistribution layer.

15. The structure of claim 11, wherein said conductive layer comprises a metallic material.

16. The structure of claim 10, wherein said semiconductor structure is part of a wafer level ball package.

17. A method of forming a semiconductor structure, comprising:

forming a plurality of semiconductor chip on a first wafer;

dicing said first wafer;

at least partially embedding said plurality of chips within a support to form a reconfigured wafer; and

forming a plurality of inductor coils, each of said inductor coils electrically coupled to a corresponding chip, at least a portion of said inductor coils overlying said support outside the lateral boundaries of said chips.

18. The method of claim 17, wherein essentially all of said inductor coils overlies said support outside the lateral boundaries of said chip.

19. The method of claim 17, further comprising, before forming said inductor coils, at least partially embedding a plurality of magnetic regions within said support, each of said inductor coils at least partially overlying a corresponding magnetic region.

20. The method of claim 19, wherein said magnetic regions are magnetic plates.

21. The method of claim 19, wherein said magnetic regions comprise a ferromagnetic material.