METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS USING A PROTECTIVE SIDEWALL SPACER

• US 20090072401A1
• Filed: 09/19/2007
• Published: 03/19/2009
• Est. Priority Date: 09/19/2007
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Purushothaman, Sampath, Arnold, John C., Sankarapandian, Muthumanickam, Spooner, Terry A., Shobha, Hosadurga K.
• Granted Patent: US 7,781,332 B2
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure.

Claims

1. A semiconductor structure comprising:

an intermetal dielectric layer including a dielectric material having a dielectric constant less than 3.0 and located on a substrate;

a metal line and a metal via of integral construction located within said intermetal dielectric layer, wherein said metal line has a substantially horizontal bottom surface adjoining said metal via; and

a densified trench bottom region comprising said dielectric material at a higher density than said intermetal dielectric layer and vertically abutting said substantially horizontal bottom surface of said metal line.

2. The semiconductor structure of claim 1, wherein said intermetal dielectric layer comprises an organosilicate dielectric material.

3. The semiconductor structure of claim 1, further comprising:

at least one semiconductor device located on said substrate; and

at least one interconnect wiring on said substrate.

4. The semiconductor structure of claim 1, further comprising a diffusion barrier dielectric layer located underneath and vertically abutting said intermetal dielectric layer.

5. The semiconductor structure of claim 4, further comprising another intermetal dielectric layer including another dielectric material having a dielectric constant less than 3.0 vertically abutting said diffusion barrier dielectric layer and a metal via located within said another intermetal dielectric layer and said diffusion barrier dielectric layer.

6. The semiconductor structure of claim 5, further comprising another metal line vertically abutting said metal via.

7. A method for fabricating an interconnect structure comprising:

forming an intermetal dielectric layer on a substrate;

forming a via hole in said intermetal dielectric layer and filling a lower portion of said via hole with a disposable via fill material;

forming a line trench in said intermetal dielectric layer over said via hole;

forming a protective spacer on sidewalls of said interconnect line trench and on sidewalls of an upper portion of said via hole, wherein said protective spacer contains one of silicon dioxide, an organosilicate material with penant alkyl, aryl or allyl groups, and organosilicate materials having linked carbo-silane bonds, and wherein at least a portion of a bottom surface of said interconnect line trench is not covered by said protective spacer; and

performing a plasma strip to remove said disposable via fill material, while said protective layer protects said intermetal dielectric layer from damage during said plasma strip.

8. The method of claim 7, further comprising:

forming a diffusion barrier dielectric layer on said substrate prior to said forming of said intermetal dielectric layer;

etching a contact hole through said diffusion barrier dielectric layer after said performing of said plasma strip; and

filling said contact hole, said via hole, and said line trench with a conductive barrier metal liner and a conductive via fill material.

9. The method of claim 8, wherein said diffusion barrier dielectric layer comprises at least one of silicon nitride, silicon carbide, and silicon-carbonitride material that is deposited by plasma enhanced chemical vapor deposition or spin on coating.

10. The method of claim 8, further comprising:

forming a hard mask on said intermetal dielectric layer;

forming an interconnect line trench in said intermetal dielectric layer over said via hole; and

planarizing said conductive barrier metal liner and said conductive via fill material.

11. The method of claim 10, wherein said hard mask layer comprises at least one material selected from silicon oxide, silicon nitride, and silicon-oxycarbide.

12. The method of claim 10, further comprising:

applying a first photolithographic resist on said hard mask and patterning said first photolithographic resist in the form of interconnect vias;

transferring a pattern in said first photolithographic resist into said hard mask and said intermetal dielectric layers by a reactive ion etch to form said via hole;

removing said first photolithographic resist;

applying a disposable via fill material to fill said via hole, wherein a top surface of said disposable via fill material is substantially coplanar with a top surface of said hardmask;

depositing a pattern transfer mask layer on said disposable via fill material;

applying a second photolithographic resist on said pattern transfer mask layer and patterning said first photolithographic resist in the form of interconnect lines; and

transferring another pattern in said second photolithographic resist into said pattern transfer mask, said disposable via fill material, said hard mask layer and into said intermetal dielectric by reactive ion etching, while concurrently consuming a portion of said disposable via fill material.

13. The method of claim 12, wherein said pattern transfer mask layer comprises at least one material selected from silicon oxide, organosilicate glass, and siloxane.

14. The method of claim 12, wherein said pattern transfer mask layer is deposited on said disposable via fill material by at least one method selected from plasma enhanced chemical vapor deposition, chemical vapor deposition, and spin coat and cure, at a temperature that does not affect composition or physical integrity of said disposable via fill material.

15. The method of claim 7, wherein said protective layer comprises at least one material selected from silicon oxide, an organosilicate materials, an organosilcate material with carbosilane functional groups containing bridged silicon-carbon-silicon bonds in chemical composition, and an organosilicate material with pendant groups selected from alkyl, allyl and aryl moieties in chemical composition, and wherein said protective layer is deposited by at least one process selected from chemical vapor deposition, plasma enhanced chemical vapor deposition, and spin coating curing employing precursors containing silane, siloxane, carbosilanes, organosiloxanes, oxygen, nitrous oxide or mixtures thereof.

16. The method of claim 7, wherein said intermetal dielectric layer comprises a porous organosilicate dielectric material, wherein said porous organosilicate dielectric material includes silicon, carbon, oxygen and hydrogen.

17. A method for fabricating an interconnect structure comprising:

forming an intermetal dielectric layer on a substrate;

forming a via hole in said intermetal dielectric layer and filling a lower portion of said via hole with a disposable via fill material;

forming a line trench in said intermetal dielectric layer over said via hole;

forming a protective spacer on sidewalls of said line trench and on sidewalls of an upper portion of said via hole, wherein said protective spacer contains one of silicon oxide, an organosilicate material, an organo-silicate material and having linked carbo-silane bonds, and an organosilicate material with pendant alkyl, aryl or allyl groups, on said intermetal dielectric layer, and wherein a portion of a bottom surface of said line trench is not covered by said protective spacer;

performing a densification treatment on said bottom surface of said line trench to form a densified trench bottom region; and

performing a plasma strip to remove said disposable via fill material, while said protective layer and said densified trench bottom region protects said intermetal dielectric layer from damage during said plasma strip.

18. The method of claim 17, wherein said densification treatment comprises at least one of bombardment by an inert gas plasma, bombardment by a gas cluster ion beam, thermal annealing, thermal annealing with simultaneous ultraviolet irradiation.

19. The method of claim 18, wherein said inert gas plasma or said gas cluster ion beam is formed from a gas containing at least one of helium, neon, argon, krypton, and xenon.

20. The method of claim 17, further comprising performing a wet clean wherein said densified trench bottom region and said protective spacer protect said intermetal dielectric layer during said wet clean.