Wiring Structure, Semiconductor Device and Manufacturing Method Thereof

• US 20090072403A1
• Filed: 09/15/2006
• Published: 03/19/2009
• Est. Priority Date: 09/16/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Hayashi, Yoshihiro, Ito, Fuminori, Takeuchi, Tsuneo
• Granted Patent: US 8,039,921 B2
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02203 the layer being porous
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/02348 treatment by exposure to UV light
• CPC Class Codes: H01L 21/02351 treatment by exposure to corpuscular radiation, e.g. exposure to electrons, alpha-particles, protons or ions
• CPC Class Codes: H01L 21/02362 formation of intermediate layers, e.g. capping layers or diffusion barriers
• CPC Class Codes: H01L 21/31695 Deposition of porous oxides or porous glassy oxides or oxide based porous glass
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 2221/1047 the air gaps being formed by pores in the dielectric
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device with a high-strength porous modified layer having a pore size of 1 nm or less, which is formed, in a multilayer wiring forming process, by forming a via hole and a wiring trench in a via interlayer insulating film and a wiring interlayer insulting film and then irradiating an electron beam or an ultraviolet ray onto the opening side walls.

Claims

1. A wiring structure of a semiconductor device formed, on a semiconductor device, with a barrier insulating film and a first porous interlayer insulating film containing pores, and having a wiring and a via plug formed by embedding a metal wiring material in a wiring trench and a via hole formed in said first porous interlayer insulating film, wherein:

a second porous interlayer insulating film is formed at least a portion of said first porous interlayer insulating film and pores contained in said second porous interlayer insulating film have a size greater than that of the pores contained in said first porous interlayer insulating film.

2. A wiring structure according to claim 1, wherein:

the size of the pores contained in said second porous interlayer insulating film is 1 nm or less.

3. A wiring structure according to claim 1, wherein:

constituent elements of said first porous interlayer insulating film are the same as those of said second porous interlayer insulating film.

4. A wiring structure according to claim 1, wherein:

said first and second porous interlayer insulating films are each in the form of a silicon oxide film containing carbon and hydrogen.

5. A wiring structure according to claim 1, wherein:

a ratio of the number of carbon atoms to the number of silicon atoms in said second porous interlayer insulating film is smaller than a ratio of the number of carbon atoms to the number of silicon atoms in said first porous interlayer insulating film and a ratio of the number of oxygen atoms to the number of silicon atoms in said second porous interlayer insulating film is greater than a ratio of the number of oxygen atoms to the number of silicon atoms in said first porous interlayer insulating film.

6. A wiring structure according to claim 1, wherein:

said second porous interlayer insulating film is formed at a side wall, surrounding said metal wiring material, of said first porous interlayer insulating film.

7. A wiring structure according to claim 1, wherein:

said second porous interlayer insulating film formed at the side wall, surrounding said metal wiring material, of said first porous interlayer insulating film has a thickness of 5 nm or more.

8. A wiring structure according to claim 1, wherein:

a third porous interlayer insulating film is formed in a surface layer of a via interlayer insulating film being said first porous interlayer insulating film surrounding a side surface of said via plug, in a surface layer of a wiring interlayer insulating film being said first porous interlayer insulating film surrounding a side surface of said wiring, or in each of both said surface layers.

9. A wiring structure according to claim 8, wherein:

said third porous interlayer insulating film formed in the surface layer of said via interlayer insulating film, in the surface layer of said wiring interlayer insulating film, or in each of both said surface layers is 5 nm or more and 30 nm or less.

10. A wiring structure according to claim 8, comprising:

said third porous interlayer insulating film of 5 nm or more and 30 nm or less formed in the surface layer of said via interlayer insulating film, in the surface layer of said wiring interlayer insulating film, or in each of both said surface layers and said second porous interlayer insulating film of 5 nm or more formed at the side wall, surrounding said metal wiring material, of said first porous interlayer insulating film.

11. A wiring structure according to claim 8, wherein:

pores contained in said third porous interlayer insulating film have a size greater than that of the pores contained in said first porous interlayer insulating film, and

the size of the pores contained in said second porous interlayer insulating film is 1 nm or less and greater than that of the pores contained in said third porous interlayer insulating film.

12. A wiring structure according to claim 1, wherein:

said wiring trench and said via hole each have a tapered shape with an opening diameter decreasing downward.

13. A wiring structure according to claim 1, wherein:

a fourth porous interlayer insulating film is formed over an entire via interlayer insulating film being said first porous interlayer insulating film surrounding a side surface of said via plug, over an entire wiring interlayer insulating film being said first porous interlayer insulating film surrounding a side surface of said wiring, or over each of both said entire via and wiring interlayer insulating films, and pores contained in said fourth porous interlayer insulating film have a size greater than that of the pores contained in said first porous interlayer insulating film.

14. A wiring structure according to claim 1, wherein:

said wiring interlayer insulating film being said first porous interlayer insulating film surrounding the side surface of said wiring is made of a material containing cyclic SiO bonds and a hydrocarbon is bonded to a side chain of said cyclic SiO bonds.

15. A wiring structure according to claim 14, wherein:

said cyclic SiO bonds form a six-membered ring or an eight-membered ring.

16. A semiconductor device, wherein:

a wiring structure according to claim 1 forms a plural-layer structure and a transistor is mounted in said plural-layer wiring structure.

17. A semiconductor device manufacturing method for manufacturing a semiconductor device having a transistor mounted in wiring of a plural-layer structure, comprising:

in manufacturing the semiconductor device formed, on a semiconductor element, with a barrier insulating film and a porous interlayer insulating film and having a wiring and a via plug formed by embedding a metal wiring material in a wiring trench and a via hole formed in said porous interlayer insulating film, irradiating an electron beam or an ultraviolet ray onto at least a portion of said porous interlayer insulating film before forming an opening in said barrier insulating film.

18. A semiconductor device manufacturing method according to claim 17, further comprising:

a step of etching said porous interlayer insulating film to form an opening and then irradiating an electron beam or an ultraviolet ray onto a side wall of said opening.

19. A semiconductor device manufacturing method according to claim 17 further comprising:

irradiating an electron beam or an ultraviolet ray after forming a via interlayer insulating film being said porous interlayer insulating film surrounding a side surface of said via plug, after forming a wiring interlayer insulating film being said porous interlayer insulating film surrounding a side surface of said wiring, or after both of said film formings.

20. A semiconductor device manufacturing method according to claim 19, comprising:

a first irradiation irradiating an electron beam or an ultraviolet ray after forming said via interlayer insulating film, after forming said wiring interlayer insulating film, or after both said film formings, and

a second irradiation etching said wiring interlayer insulating film and said via interlayer insulating film to form an opening and then irradiating an electron beam or an ultraviolet ray onto a side wall of said opening.

21. A semiconductor device manufacturing method according to claim 17, wherein:

an arrival energy of electrons in the irradiating of the electron beam is 0.25 keV or more and 20 keV or less.

22. A semiconductor device manufacturing method according to claim 17, wherein:

a wavelength of ultraviolet light in the irradiating of the ultraviolet ray is 150 nm to 275 nm.

23. A semiconductor device manufacturing method according to claim 17, wherein:

a temperature of a substrate of the semiconductor device in the irradiating of the electron beam or the ultraviolet ray is set to 200°

C. to 450°

C.

24. A semiconductor device manufacturing method according to claim 17, wherein:

irradiation is performed by inclining and rotating a substrate of the semiconductor device in the irradiating of the electron beam or the ultraviolet ray.

25. A semiconductor device manufacturing method according to claim 17, wherein:

an insulating film having a pore size smaller than that of a via interlayer insulating film being said porous interlayer insulating film surrounding a side surface of said via plug, or an insulating film in which a ratio of the number of carbon atoms to the number of silicon atoms is greater than that in said via interlayer insulating film is applied to at least a wiring interlayer insulating film being said porous interlayer insulating film surrounding a side surface of said wiring.

26. A semiconductor device manufacturing method according to claim 25, wherein:

said wiring interlayer insulating film has a pore size of 0.5 nm or less.

27. A semiconductor device manufacturing method according to claim 25, wherein:

the ratio of the number of carbon atoms to the number of silicon atoms in said wiring interlayer insulating film is three or more.

28. A semiconductor device manufacturing method according to claim 25, wherein:

said wiring interlayer insulating film is made of a material containing cyclic SiO bonds and a hydrocarbon is bonded to a side chain of said cyclic SiO bonds.

29. A semiconductor device manufacturing method according to claim 28, wherein:

said cyclic SiO bonds form a six-membered ring or an eight-membered ring.