Circuit Arrangement and Method for the Provision of a Clock Signal with an Adjustable Duty Cycle
First Claim
1. A circuit arrangement for the provision of a clock signal with an adjustable cycle comprising:
- an input for connecting an oscillator;
an amplifier circuitwith a first input that is coupled to the input of the circuit arrangement;
with a second input;
with a comparator whose inputs constitute the first and second input of the amplifier circuit; and
with a buffer that comprises at least a first inverter and couples an output of the comparator to an output of the amplifier circuit;
an output which is connected to the output of the amplifier circuit and at which a clock signal with a duty cycle is available;
a low-pass filter, an input of which is connected to the output of the amplifier circuit; and
an integrator circuit, an input of which is connected to the low-pass filter and an output of which is connected to the second input of the amplifier circuit for the provision of an adjustable threshold value for controlling the duty cycle (f);
wherein the integrator circuit comprises a loop filter that is connected to the output of the integrator circuit; and
wherein the loop filter comprises a first capacitor that connects the output of the integrator circuit to the ground potential terminal and a series circuit comprising a resistor and a second capacitor that connect the output of the integrator circuit to the ground potential terminal.
1 Assignment
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Accused Products
Abstract
The circuit arrangement (1) comprises an input (2) for the connection of an oscillator (3) and an amplifier circuit (20) having a first input (21) that is coupled to the input (1) of the circuit arrangement (1), having a second input (22) and an output (23) that is connected to an output (4) of the circuit arrangement (1). A clock signal (Vout) with a duty cycle (φ) can be accessed at the output (4) of the circuit arrangement (1) The circuit arrangement (1) furthermore incorporates a low-pass filter (40), the input of which is connected to the output (23) of the amplifier circuit (20), and an integrator circuit (50) the input of which is connected to the low-pass filter (40) and the output of which is connected to the second input (22) of the amplifier circuit (20) for the delivery of an adjustable threshold value (Vth) for controlling the duty cycle (φ).
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Citations
20 Claims
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1. A circuit arrangement for the provision of a clock signal with an adjustable cycle comprising:
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an input for connecting an oscillator; an amplifier circuit with a first input that is coupled to the input of the circuit arrangement; with a second input; with a comparator whose inputs constitute the first and second input of the amplifier circuit; and with a buffer that comprises at least a first inverter and couples an output of the comparator to an output of the amplifier circuit; an output which is connected to the output of the amplifier circuit and at which a clock signal with a duty cycle is available; a low-pass filter, an input of which is connected to the output of the amplifier circuit; and an integrator circuit, an input of which is connected to the low-pass filter and an output of which is connected to the second input of the amplifier circuit for the provision of an adjustable threshold value for controlling the duty cycle (f); wherein the integrator circuit comprises a loop filter that is connected to the output of the integrator circuit; and wherein the loop filter comprises a first capacitor that connects the output of the integrator circuit to the ground potential terminal and a series circuit comprising a resistor and a second capacitor that connect the output of the integrator circuit to the ground potential terminal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for providing a clock signal with an adjustable duty cycle, comprising the steps of:
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supplying an oscillator signal; comparing the oscillator signal with a threshold value, amplifying the result of the comparison and providing the amplified result of the comparison as the clock signal with the duty cycle; providing a signal derived from the duty cycle; and comparing the signal derived from the duty cycle with an adjustable reference voltage and providing the threshold value in accordance with the result of the comparison; wherein an integrator circuit comprises a transconductance amplifier and a loop filter, the integrator circuit provides at its output the threshold value depending on a current at an output of the transconductance amplifier and on a filter characteristic of the loop filter, and where the loop filter comprises a first capacitor that is connected in parallel to a series circuit comprising a second capacitor and a first resistor between the output of the transconductance amplifier and a ground potential terminal.
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13. A circuit arrangement for the provision of a clock signal with an adjustable duty cycle, comprising:
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an input for the connection of an oscillator; an amplifier circuit comprising; a first input that is coupled to the input of the circuit arrangement, a second input, a comparator whose inputs form the first and second inputs of the amplifier circuit, and a buffer that comprises at least a first inverter and which couples an output of the comparator to an output of the amplifier circuit; an output that is coupled to the output of the amplifier circuit and where a clock signal with a duty cycle can be accessed; a low-pass filter, an input of which is coupled to the output of the amplifier circuit; and an integrator circuit, an input of which is coupled to the low-pass filter and an output of which is coupled to the second input of the amplifier circuit to deliver an adjustable threshold value to control the duty cycle. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification