RADAR APPARATUS

• US 20090073029A1
• Filed: 10/27/2008
• Published: 03/19/2009
• Est. Priority Date: 06/02/2006
• Status: Active Grant

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: NISHIJIMA, Masaaki, FUKUDA, Takeshi
• Granted Patent: US 7,609,199 B2
• Time in Patent Office: Days
• US Class Current: 342/200
• CPC Class Codes: G01S 13/325 using transmission of coded signals, e.g. P.S.K. signals
• CPC Class Codes: G01S 7/03 Details of HF subsystems specially adapted therefor, e.g. common to transmitter and receiver
• CPC Class Codes: G01S 7/35 Details of non-pulse systems

Abstract

A radar apparatus includes a PN code generator for generating a PN code, a variable delay device for delaying the PN code, an oscillator for generating a high-frequency signal, a transmission frequency multiplier for multiplying a frequency of a transmission differential signal obtained by being divided from the high-frequency signal by 3, a reception frequency multiplier for multiplying a frequency of a reception differential signal obtained by being divided from the high-frequency by 3, a transmitter for generating a radar wave by using the differential signal obtained through the multiplication by the transmission frequency multiplier and the PN code generated by the PN code generator, and a receiver for generating an in-phase signal and a quadrature signal from a reflected wave by using the differential signal obtained through the multiplication by the reception frequency multiplier and the PN code delayed by the delay device.

Claims

1. A radar apparatus that transmits a radar wave, receives a reflected wave obtained through reflection of the radar wave off an object, and detects the object from the reflected wave, said radar apparatus comprising:

an oscillator that generates a high-frequency signal;

a transmission multiplier, made up of a differential circuit for inputting and outputting a differential signal, to which a high-frequency signal divided for transmission from the high-frequency signal generated by said oscillator is inputted as a transmission differential signal which is the differential signal, and which multiplies a frequency of the transmission differential signal by a predetermined multiplication ratio, the differential signal being made up of a positive-side signal and a negative-side signal;

a reception multiplier, made up of the differential circuit, to which a high-frequency signal divided for reception from the high-frequency signal generated by said oscillator is inputted as a reception differential signal which is the differential signal, and which multiplies a frequency of the reception differential signal by the same multiplication ratio as with said transmission multiplier;

a transmitter which generates the radar wave from the differential signal obtained through the multiplication by said transmission multiplier; and

a receiver which generates a demodulated signal;

from the reflected wave, and the differential signal obtained through the multiplication by said reception multiplier.

2. The radar apparatus according to claim 1, wherein said transmission multiplier includes a differential amplifier circuit having a set of a first amplifier circuit and a second amplifier circuit, the first amplifier circuit being made up of a first transistor and a second transistor which are cascode-connected, and the second amplifier circuit being made up of a third transistor and a fourth transistor which are cascode-connected, and a virtual ground of said first amplifier circuit and a virtual ground of said second amplifier circuit are electrically connected, via a via hole, with a ground layer formed on a backside of a semiconductor substrate on which said differential amplifier circuit is formed.

3. The radar apparatus according to claim 1, wherein said transmission multiplier includes a differential amplifier circuit having a set of a first amplifier circuit and a second amplifier circuit, the first amplifier circuit being made up of a first transistor and a second transistor which are cascode-connected, and the second amplifier circuit being made up of a third transistor and a fourth transistor which are cascode-connected, and a virtual ground of the first amplifier circuit and a virtual ground of the second amplifier circuit are electrically connected, via a via hole, with a ground layer formed in a layer portion lower than a portion in which said differential amplifier circuit is formed, in a semiconductor substrate on which said differential amplifier circuit is formed.

4. The radar apparatus according to claim 1, wherein said transmission multiplier includes a differential amplifier circuit having a set of a first amplifier circuit and a second amplifier circuit, the first amplifier circuit being made up of a first transistor and a second transistor which are cascode-connected, and the second amplifier circuit being made up of a third transistor and a fourth transistor which are cascode-connected, and a virtual ground of said first amplifier circuit and a virtual ground of said second amplifier circuit are electrically connected, via a via hole, with a ground layer formed in a layer portion higher than a portion in which said differential amplifier circuit is formed, in a semiconductor substrate on which said differential amplifier circuit is formed.

5. The radar apparatus according to claim 1, wherein said transmission multiplier comprises:

an input buffer circuit which generates, from the transmission differential signal, a first differential signal and a second differential signal having a phase difference of 90 degrees from the first differential signal;

a Gilbert cell mixer which mixes the first differential signal and the second differential signal generated by said input buffer circuit; and

an output buffer circuit which amplifies a third differential signal obtained through the mixing by said Gilbert cell mixer.

6. The radar apparatus according to claim 5, wherein said input buffer circuit is made up of at least one transistor, and generates the first differential signal and the second differential signal, said Gilbert cell mixer being made up of at least one transistor, and generates the third differential signal from the first differential signal and the second differential signal, and said transmission multiplier comprises:

a first bias terminal to which a signal for adjusting a bias of at least one transistor is inputted, the at least one transistor making up said input buffer circuit and being inputted with the positive-side signal of the transmission differential signal; and

a second bias terminal to which a signal for adjusting a bias of at least one transistor is inputted, the at least one transistor making up said input buffer circuit and being inputted with the negative-side signal of the transmission differential signal.

7. The radar apparatus according to claim 5, wherein said input buffer circuit is made up of a polyphase filter, and generates the first differential signal and the second differential signal, said Gilbert cell mixer is made up of at least one transistor, and generates a third differential signal from the first differential signal and the second differential signal, and said transmission multiplier comprises:

a first bias terminal to which a signal for adjusting a bias of at least one transistor is inputted, the at least one transistor making up said Gilbert cell mixer and being inputted with the positive-side signal of the first differential signal;

a second bias terminal to which a signal for adjusting a bias of at least one transistor is inputted, the at least one transistor making up said Gilbert cell mixer and being inputted with the negative-side signal of the first differential signal;

a third bias terminal to which a signal for adjusting a bias of at least one transistor is inputted, the at least one transistor making up said Gilbert cell mixer and being inputted with the positive-side signal of the second differential signal; and

a fourth bias terminal to which a signal for adjusting a bias of at least one transistor is inputted, the at least one transistor making up said Gilbert cell mixer and being inputted with the negative-side signal of the second differential signal.

8. The radar apparatus according to claim 1, wherein the high-frequency signal generated by said oscillator comprises a single-ended signal, and said radar apparatus comprises a conversion circuit which converts the single-ended signal generated by said oscillator into the differential signal, and outputs the differential signal to said transmission multiplier and said reception multiplier.

9. The radar apparatus according to claim 1, further comprising a transmission amplifier which amplifies the differential signal obtained through the multiplication by said transmission multiplier, and outputs the amplified differential signal to said transmitter.

10. The radar apparatus according to claim 1, wherein said reception multiplier includes a differential amplifier circuit having a set of a first amplifier circuit and a second amplifier circuit, the first amplifier circuit being made up of a first transistor and a second transistor which are cascode-connected, and the second amplifier circuit being made up of a third transistor and a fourth transistor which are cascode-connected, and a virtual ground of the first amplifier circuit and a virtual ground of the second amplifier circuit are electrically connected, via a via hole, with a ground layer formed on a backside of a semiconductor substrate on which said differential amplifier circuit is formed.

11. The radar apparatus according to claim 1, wherein said reception multiplier includes a differential amplifier circuit having a set of a first amplifier circuit and a second amplifier circuit, the first amplifier circuit being made up of a first transistor and a second transistor which are cascode-connected, and the second amplifier circuit being made up of a third transistor and a fourth transistor which are cascode-connected, and a virtual ground of the first amplifier circuit and a virtual ground of the second amplifier circuit are electrically connected, via a via hole, with a ground layer formed in a layer portion lower than a portion in which said differential amplifier circuit is formed, in a semiconductor substrate on which said differential amplifier circuit is formed.

12. The radar apparatus according to claim 1, wherein said reception multiplier includes a differential amplifier circuit having a set of a first amplifier circuit and a second amplifier circuit, the first amplifier circuit being made up of a first transistor and a second transistor which are cascode-connected, and the second amplifier circuit being made up of a third transistor and a fourth transistor which are cascode-connected, and a virtual ground of said first amplifier circuit and a virtual ground of said second amplifier circuit are electrically connected, via a via hole, with a ground layer formed in a layer portion higher than a portion in which said differential amplifier circuit is formed, in a semiconductor substrate on which said differential amplifier circuit is formed.

13. The radar apparatus according to claim 1, wherein said reception multiplier comprises:

an input buffer circuit which generates, from the reception differential signal, a first differential signal and a second differential signal having a phase difference of 90 degrees from the first differential signal;

a Gilbert cell mixer which mixes the first differential signal and the second differential signal generated by said input buffer circuit; and

an output buffer circuit which amplifies a third differential signal obtained through the mixing by said Gilbert cell mixer.

14. The radar apparatus according to claim 13,

wherein said input buffer circuit is made up of at least one transistor, and generates the first differential signal and the second differential signal, said Gilbert cell mixer is made up of at least one transistor, and generates the third differential signal from the first differential signal and the second differential signal, and said reception multiplier comprises:

a first bias terminal to which a signal for adjusting a bias of at least one transistor is inputted, the at least one transistor making up said input buffer circuit and being inputted with the positive-side signal of the reception differential signal; and

a second bias terminal to which a signal for adjusting a bias of at least one transistor is inputted, the at least one transistor making up said input buffer circuit and being inputted with the negative-side signal of the reception differential signal.

15. The radar apparatus according to claim 13, wherein said input buffer circuit is made up of a polyphase filter, and generates the first differential signal and the second differential signal, said Gilbert cell mixer is made up of at least one transistor, and generates the third differential signal from the first differential signal and the second differential signal, and said reception multiplier comprises:

a first bias terminal to which a signal for adjusting a bias of at least one transistor is inputted, the at least one transistor making up said Gilbert cell mixer and being inputted with the positive-side signal of the first differential signal;

a second bias terminal to which a signal for adjusting a bias of at least one transistor is inputted, the at least one transistor making up said Gilbert cell mixer and being inputted with the negative-side signal of the first differential signal;

a third bias terminal to which a signal for adjusting a bias of at least one transistor is inputted, the at least one transistor making up said Gilbert cell mixer and being inputted with the positive-side signal of the second differential signal; and

a fourth bias terminal to which a signal for adjusting a bias of at least one transistor is inputted, the at least one transistor making up said Gilbert cell mixer and being inputted with the negative-side signal of the second differential signal.

16. The radar apparatus according to claim 1, further comprising a reception amplifier which amplifies the differential signal obtained through the multiplication by said reception multiplier, and outputs the amplified differential signal to said receiver.