SIGNAL CONTROL CIRCUIT AND METHOD THEREOF, LIQUID CRYSTAL DISPLAY AND TIMING CONTROLLER THEREOF
First Claim
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1. A signal control circuit, comprising:
- a bus, for transmitting a low voltage differential signal (LVDS) clock; and
a control unit, comprising a transistor having a source, a drain and a gate, wherein the source is electrically connected to a reference level, the gate is used for receiving the LVDS clock, and the drain is electrically connected a supply voltage and is suitable for outputting a driving signal,wherein when a voltage level of a common-mode voltage of the LVDS clock drops to the reference level, a voltage level of the driving signal is maintained to the supply voltage.
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Abstract
A signal control circuit and a method thereof, and a liquid crystal display (LCD) and a timing controller thereof are provided. The signal control circuit of the present invention maintains a voltage level of a driving signal output from the timing controller for driving data drivers to the supply voltage, such that the data drivers may cease outputting display data to the liquid crystal display panel when the LCD is turned off. Therefore, the image sticking, ghost image and fan-out phenomenon occurred when the LCD is turned off may be avoided.
9 Citations
25 Claims
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1. A signal control circuit, comprising:
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a bus, for transmitting a low voltage differential signal (LVDS) clock; and a control unit, comprising a transistor having a source, a drain and a gate, wherein the source is electrically connected to a reference level, the gate is used for receiving the LVDS clock, and the drain is electrically connected a supply voltage and is suitable for outputting a driving signal, wherein when a voltage level of a common-mode voltage of the LVDS clock drops to the reference level, a voltage level of the driving signal is maintained to the supply voltage. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A signal control method, comprising:
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detecting a voltage level of a common-mode voltage of an LVDS clock supplied to a timing controller; and maintaining a voltage level of a driving signal output from the timing controller for driving a data driver to a supply voltage when the voltage level of the common-mode voltage drops to a reference level. - View Dependent Claims (8, 9)
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10. A liquid crystal display (LCD), comprising:
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a signal control circuit, for detecting a voltage level of a common-mode voltage of an LVDS clock, so as to maintain a voltage level of a driving signal to a supply voltage when the voltage level of the common-mode voltage drops to a reference level; a plurality of data drivers, electrically connected to the signal control circuit, wherein each of the data drivers receive the driving signal maintained to the supply voltage when the voltage level of the common-mode voltage drops to the reference level, so as to cease outputting a corresponding display data; and an LCD panel, electrically connected to the data drivers, for correspondingly receiving the display data output from each of the data drivers to display an image, and quickly dissipating residual charges within pixel array of the LCD panel when the voltage level of the common-mode voltage drops to the reference level. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A timing controller, characterized by:
at least one flip-flop, for controlling a voltage level of a driving signal output from the timing controller for driving a data driver to be maintained to a supply voltage when a voltage level of a common-mode voltage of an LVDS clock received by the timing controller drops to a reference level, wherein the reference level comprises a ground level, and the supply voltage comprises a high level voltage. - View Dependent Claims (21)
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22. A liquid crystal display (LCD), comprising:
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a plurality of data drivers, each of the data drivers receiving a corresponding driving signal, an image signal and a clock signal; a timing controller, electrically connected to the data drivers and comprising at least one flip-flop, wherein the timing controller being used for receiving and processing an LVDS clock and an LVDS data transmitted from a bus to individually provide the clock signal, the image signal and the driving signal to the corresponding data drivers; and an LCD panel, electrically connected to the data drivers, for correspondingly receiving a display data output from each of the data drivers to display an image, wherein when a voltage level of a common-mode voltage of the LVDS clock received by the timing controller drops to a reference level, a voltage level of the driving signal is maintained to a supply voltage under control of the flip-flop, and each of the data drivers receives the driving signal maintained to the supply voltage to cease outputting the display data, such that residual charges within pixel array of the LCD panel is quickly dissipated. - View Dependent Claims (23, 24, 25)
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Specification