SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND ELECTRIC DEVICE

• US 20090073325A1
• Filed: 11/11/2008
• Published: 03/19/2009
• Est. Priority Date: 01/21/2005
• Status: Abandoned Application

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KUWABARA, Hideaki, YAMAMOTO, Hiroko
• Application Number:
  US12/268,558
• Publication Number:
  US 20090073325A1
• Time in Patent Office: Days
• US Class Current: 348/790
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/49855 for flat-cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

It is an object of the present invention to simplify steps needed to process a wiring in forming a multilayer wiring. In addition, when a droplet discharging technique or a nanoimprint technique is used to form a wiring in a contact hole having a comparatively long diameter, the wiring in accordance with the shape of the contact hole is formed, and the wiring portion of the contact hole is likely to have a depression compared with other portions. A penetrating opening is formed by irradiating a light-transmitting insulating film with laser light having high intensity and a pulse high in repetition frequency. A plurality of openings having a minute contact area is provided instead of forming one penetrating opening having a large contact area to have an even thickness of a wiring by reducing a partial depression and also to ensure contact resistance.

Claims

1. A active matrix display device comprising:

a thin film transistor formed over a substrate, the thin film transistor comprising a semiconductor layer wherein the semiconductor layer comprises a metal oxide including at least indium; and

a pixel electrode formed over the substrate and electrically connected to the thin film transistor.

2. The active matrix display device according to claim 1, wherein the metal oxide includes zinc, gallium, and indium.

3. The active matrix display device according to claim 1, wherein the thin film transistor is a bottom gate thin film transistor.

4. The active matrix display device according to claim 1, wherein the thin film transistor is a top gate thin film transistor.

5. The active matrix display device according to claim 1, wherein the active matrix display device is a liquid crystal display device.

6. The active matrix display device according to claim 1, wherein the active matrix display device is an EL display device.

7. The active matrix display device according to claim 1, wherein the substrate is a plastic substrate.

8. The active matrix display device according to claim 1, further comprising an interlayer insulating film formed over the thin film transistor wherein the pixel electrode is electrically connected to the thin film transistor though a plurality of openings formed in the interlayer insulating film.

9. An active matrix display device comprising:

a thin film transistor formed over a substrate; and

a pixel electrode formed over the substrate and electrically connected to the thin film transistor,

the thin film transistor including;

at least two gate electrodes electrically connected to each other;

a gate insulating film formed over at least the two gate electrodes; and

a semiconductor layer formed over the gate insulating film so as to overlap the two gate electrodes wherein the semiconductor layer comprises a metal oxide including at least indium.

10. The active matrix display device according to claim 9, wherein the metal oxide includes zinc, gallium, and indium.

11. The active matrix display device according to claim 9, further comprising a wiring over the semiconductor layer wherein the pixel electrode is connected to the wiring.

12. The active matrix display device according to claim 9, wherein the thin film transistor is a top gate thin film transistor.

13. The active matrix display device according to claim 9, wherein the active matrix display device is a liquid crystal display device.

14. The active matrix display device according to claim 9, wherein the active matrix display device is an EL display device.

15. The active matrix display device according to claim 9, wherein the substrate is a plastic substrate.

16. The active matrix display device according to claim 9, further comprising an interlayer insulating film formed over the thin film transistor wherein the pixel electrode is electrically connected to the thin film transistor through a plurality of openings formed in the interlayer insulating film.

17. A television device comprising:

a tuner for receiving a video signal;

a video signal processing circuit operationally connected to the tuner; and

an active matrix display device operationally connected to the video signal processing circuit, the active matrix display device comprising;

a thin film transistor formed over a substrate, the thin film transistor comprising a semiconductor layer wherein the semiconductor layer comprises a metal oxide including at least indium; and

a pixel electrode formed over the substrate and electrically connected to the thin film transistor.

18. The television device according to claim 17, wherein the metal oxide includes zinc, gallium, and indium.

19. The television device according to claim 17, wherein the thin film transistor is a bottom gate thin film transistor.

20. The television device according to claim 17, wherein the thin film transistor is a top gate thin film transistor.

21. The television device according to claim 17, wherein the active matrix display device is a liquid crystal display device.

22. The television device according to claim 17, wherein the active matrix display device is an EL display device.

23. The television device according to claim 17, wherein the substrate is a plastic substrate.

24. The television device according to claim 17, further comprising an interlayer insulating film formed over the thin film transistor wherein the pixel electrode is electrically connected to the thin film transistor though a plurality of openings formed in the interlayer insulating film.

25. A television device comprising:

a tuner for receiving a video signal;

a video signal processing circuit operationally connected to the tuner; and

an active matrix display device operationally connected to the video signal processing circuit, the active matrix display device comprising;

a thin film transistor formed over a substrate, and

a pixel electrode formed over the substrate and electrically connected to the thin film transistor,

the thin film transistor including;

at least two gate electrodes electrically connected to each other;

a gate insulating film formed over at least the two gate electrodes; and

a semiconductor layer formed over the gate insulating film so as to overlap the two gate electrodes wherein the semiconductor layer comprises a metal oxide including at least indium.

26. The television device according to claim 25, wherein the metal oxide includes zinc, gallium, and indium.

27. The television device according to claim 25, further comprising a wiring over the semiconductor layer wherein the pixel electrode is connected to the wiring.

28. The television device according to claim 25, wherein the thin film transistor is a top gate thin film transistor.

29. The television device according to claim 25, wherein the active matrix display device is a liquid crystal display device.

30. The television device according to claim 25, wherein the active matrix display device is an EL display device.

31. The television device according to claim 25, wherein the substrate is a plastic substrate.

32. The television device according to claim 25, further comprising an interlayer insulating film formed over the thin film transistor wherein the pixel electrode is electrically connected to the thin film transistor through a plurality of openings formed in the interlayer insulating film.

33. A active matrix display device comprising:

a bottom gate type thin film transistor formed over a substrate, the bottom gate type thin film transistor comprising a semiconductor layer wherein the semiconductor layer comprises a metal oxide including zinc, gallium, and indium; and

a pixel electrode formed over the substrate and electrically connected to the thin film transistor.

34. The active matrix display device according to claim 33, wherein the active matrix display device is a liquid crystal display device.

35. The active matrix display device according to claim 33, wherein the active matrix display device is an EL display device.

36. The active matrix display device according to claim 33, wherein the substrate is a plastic substrate.

37. A active matrix display device comprising:

a thin film transistor formed over a substrate, the thin film transistor comprising a semiconductor layer wherein the semiconductor layer comprises a metal oxide including at least indium;

a pixel electrode formed over the substrate and electrically connected to the thin film transistor; and

a driver circuit comprising an IC chip operationally connected to the thin film transistor.

38. The active matrix display device according to claim 37, wherein the metal oxide includes zinc, gallium, and indium.

39. The active matrix display device according to claim 37, wherein the active matrix display device is a liquid crystal display device.

40. The active matrix display device according to claim 37, wherein the active matrix display device is an EL display device.

41. The active matrix display device according to claim 37, wherein the substrate is a plastic substrate.

42. The active matrix display device according to claim 37, wherein the IC chip is mounted on the substrate.

43. The active matrix display device according to claim 37, wherein the driver circuit is a scanning-line driver circuit.

44. The active matrix display device according to claim 37, wherein the driver circuit is a signal-line driver circuit.