METHOD FOR CONTROLLING A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20090073763A1
• Filed: 09/12/2008
• Published: 03/19/2009
• Est. Priority Date: 09/14/2007
• Status: Active Grant

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hosono, Koji
• Granted Patent: US 7,916,547 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2211/565 Multilevel memory comprising elements in triple well structure

Abstract

A non-volatile semiconductor memory device has a NAND string, in which multiple memory cells are connected in series. A read procedure is performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof. In the read procedure, a first read pass voltage is applied to unselected memory cells except an adjacent and unselected memory cell disposed adjacent to the selected memory cell, the adjacent and unselected memory cell being completed in data write later than the selected memory cell, and a second read pass voltage higher than the first read pass voltage is applied to the adjacent and unselected memory cell.

Claims

1. A method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, comprising a read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof, wherein

a first read pass voltage is applied to unselected memory cells except an adjacent and unselected memory cell disposed adjacent to the selected memory cell, the adjacent and unselected memory cell being completed in data write later than the selected memory cell, and a second read pass voltage higher than the first read pass voltage is applied to the adjacent and unselected memory cell in the read procedure.

2. The method according to claim 1, wherein

the second read pass voltage is applied to two adjacent and unselected memory cells disposed adjacent to the selected memory cell.

3. The method according to claim 1, wherein

the read procedure is a normal read procedure for reading data of the selected memory cell after data writing.

4. The method according to claim 1, wherein

the read procedure is a write-verify read procedure for verify-reading data of the selected memory cell in a data write mode.

5. The method according to claim 3, wherein

in the normal read procedure, the second read pass voltage is applied to one cell in two adjacent and unselected memory cells disposed adjacent to the selected memory cell, the one cell having been written previously to the selected memory cell;

and a third pass voltage is applied to the other cell in the two adjacent and unselected memory cells, the other cell having been written later than the selected memory cell, the third read pass voltage being selected in level in accordance with the cell'"'"'s threshold shift amount.

6. The method according to claim 5, wherein

the third read pass voltage is set to be lower than the first read pass voltage in case the cell'"'"'s threshold shift amount is less than a certain level while the third read pass voltage is set to be equal to the second read pass voltage in case the cell'"'"'s threshold shift amount is greater than the certain level.

7. The method according to claim 5, wherein

the normal read procedure includes:

a first read operation performed for reading data of the other cell previously to reading data of the selected memory cell when it is selected; and

a second read operation performed for reading data of the selected memory cell on the condition that the third read pass voltage is selected in level with reference to the read data of the first read operation.

8. The method according to claim 1, wherein

the memory cell stores four-level data defined by data level E, A, B and C (where, E<

A<

B<

C), data level E being defined as an erase state with a negative cell threshold while data levels A, B and C are defined as write states with positive cell threshold voltages, and

data write procedure includes;

a lower page write mode for selectively writing the memory cells with data level E to have a medium level LM set between data level A and B; and

an upper page write mode for selectively writing the memory cells with data level E and data level LM to have data level A and data level B or C, respectively, and

in the data write procedure, the memory cells in the NAND string are selected from a source line side in such an order that a first memory cell is written in a lower page write mode;

a second memory cell adjacent to the first memory cell disposed adjacent to the first memory cell on a bit line side is written in the successive lower page write mode; and

then the first memory cell is written in an upper page write mode.

9. A method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, comprising a write-verifying procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof;

and a normal read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein

in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except two adjacent and unselected memory cells disposed adjacent to the selected memory cell;

a second read pass voltage higher than the first read pass voltage is applied to one cell of the two adjacent and unselected memory cells, the one cell having been written previously to the selected memory cell; and

a third read pass voltage lower than the first read pass voltage is applied to the other cell, which is written later than the selected memory cell, and

in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the two adjacent and unselected memory cells;

the second read pass voltage higher than the first read pass voltage is applied to one cell of the two adjacent and unselected memory cells, the one cell having been written previously to the selected memory cell; and

a fourth read pass voltage is applied to the other cell, which has been written later than the selected memory cell, the fourth read pass voltage being selected in level in accordance with the cell'"'"'s threshold shift amount.

10. The method according to claim 9, wherein

the fourth read pass voltage is set to be lower than the first read pass voltage in case the cell'"'"'s threshold shift amount is less than a certain level while the fourth read pass voltage is set to be equal to the second read pass voltage in case the cell'"'"'s threshold shift amount is greater than the certain level.

11. The method according to claim 10, wherein

the normal read procedure includes:

a first read operation performed for reading data of the other cell previously to reading data of the selected memory cell when it is selected; and

a second read operation performed for reading data of the selected memory cell on the condition that the fourth read pass voltage is selected in level with reference to the read data of the first read operation.

12. The method according to claim 9, wherein

the memory cell stores four-level data defined by data level E, A, B and C (where, E<

A<

B<

C), data level E being defined as an erase state with a negative cell threshold while data levels A, B and C are defined as write states with positive cell threshold voltages, and

data write procedure includes;

a lower page write mode for selectively writing the memory cells with data level E to have a medium level LM set between data level A and B; and

an upper page write mode for selectively writing the memory cells with data level E and data level LM to have data level A and data level B or C, respectively, and

in the data write procedure, the memory cells in the NAND string are selected from a source line side in such an order that a first memory cell is written in a lower page write mode;

a second memory cell adjacent to the first memory cell disposed adjacent to the first memory cell on a bit line side is written in a successive lower page write mode; and

then the first memory cell is written in a upper page write mode.

13. A method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, comprising a write-verifying procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof;

and a normal read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein

in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except adjacent and unselected memory cells adjacent to the selected memory cell;

a second read pass voltage lower than the first read pass voltage is applied to one of the adjacent and unselected memory cells, which is written later than the selected memory cell, and

in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the adjacent and unselected memory cells disposed adjacent to the selected memory cell;

a third read pass voltage is applied to one of the adjacent and unselected memory cells, which has been written later than the selected memory cell, the third read voltage being selected in level in accordance with the cell'"'"'s threshold shift amount, the maximum vale of which is higher than the first read pass voltage.

14. The method according to claim 13, wherein

the memory cell stores four-level data defined by data level E, A, B and C (where, E<

A<

B<

C), data level E being defined as an erase state with a negative cell threshold while data levels A, B and C are defined as write states with positive cell threshold voltages, and

data write procedure includes;

a lower page write mode for selectively writing the memory cells with data level E to have a medium level LM set between data level A and B; and

an upper page write mode for selectively writing the memory cells with data level E and data level LM to have data level A and data level B or C, respectively, and

in the data write procedure, the memory cells in the NAND string are selected from a source line side in such an order that a first memory cell is written in a lower page write mode;

a second memory cell adjacent to the first memory cell disposed adjacent to the first memory cell on a bit line side is written in a successive lower page write mode; and

then the first memory cell is written in a upper page write mode.