NETWORK RECEIVE INTERFACE FOR HIGH BANDWIDTH HARDWARE-ACCELERATED PACKET PROCESSING

• US 20090073884A1
• Filed: 12/01/2008
• Published: 03/19/2009
• Est. Priority Date: 02/14/2003
• Status: Active Grant

• Current Assignee: Promise Technology Incorporated
• Original Assignee: iStor Networks Incorporated (Promise Technology Incorporated)
• Inventors: Kodama, Jean, Xu, Li
• Granted Patent: US 7,869,355 B2
• Time in Patent Office: Days
• US Class Current: 370/235
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/193 at the transport layer, e.g. TCP related
• CPC Class Codes: H04L 47/22 Traffic shaping
• CPC Class Codes: H04L 47/27 Evaluation or update of window size, e.g. using information derived from acknowledged [ACK] packets
• CPC Class Codes: H04L 47/34 ensuring sequence integrity, e.g. using sequence numbers
• CPC Class Codes: H04L 69/12 Protocol engines

Abstract

Disclosed is a system and methods for accelerating network packet processing for devices configured to process network traffic at relatively high data rates. The system incorporates a hardware-accelerated packet processing module that handles in-sequence network packets and a software-based processing module that handles out-of-sequence and exception case network packets.

Claims

1. A system for network packet processing comprising:

a packet reception subsystem configure to receive network packets comprising common case network packets and non-common case network packets;

a fast-path acceleration subsystem configured to process the common case network packets using a hardware acceleration component; and

a slow-path subsystem configured to process the non-common case network packets using software-based code executed on one or more general purpose processors.

2. The system of claim 1, wherein the common case network packets comprise in-sequence network packets

3. The system of claim 1, wherein the non-common case network packets comprise infrequent case network packets.

4. The system of claim 1, wherein the non-common case network packets comprise exception case network packets.

5. The system of claim 1, wherein the non-common case network packets comprise out-of-sequence network packets.

6. The system of claim 1, wherein the slow-path subsystem is coupled with limited hardware acceleration.

7. The system of claim 6, wherein the slow-path subsystem is coupled to the fast path acceleration subsystem such that after processing of the non-common case network packets in slow-path subsystem, the network packets are subsequently processed by the fast-path acceleration subsystem.

8. The system of claim 1, wherein the fast-path acceleration subsystem is configured to process network packets arriving concurrently on one or more network ports.

9. The system of claim 1, wherein the fast path acceleration subsystem is configured to operate at approximately line rate and avoid stalls while processing packets in a pipelined manner.

10. The system of claim 1, wherein the fast-past and slow-path subsystems are configured to operate with a plurality of networking protocols.

11. The system of claim 1, wherein network packets are transmitted in a network where Ethernet is employed as a layer 2 protocol and IP is employed as a layer 3 protocol according to OSI nomenclature for networking protocols.

12. The system of claim 1, wherein the network packets comprise TCP/IP and iSCSI components that are simultaneously resolved using the fast-path and slow-path subsystems.

13. The system of claim 1k, further comprising a parser component configured to parse a plurality of incoming network packet streams, demarcate network packet boundaries, identify underlying network protocols, and categorize the network packets for fast-path or slow-path processing.

14. The system of claim 13, wherein the incoming network packet streams originate from a plurality of network ports.

15. The system of claim 1, further comprising an ingress buffer configured to buffer incoming packets as necessary to maintain processing throughput.

16. The system of claim 1, further comprising a dispatcher configured to route network packets to the fast-path and slow-path subsystems.

17. The system of claim 1, wherein network packets processed by the slow-path subsystem are relatively quickly returned to the fast-path subsystem to improve networking performance.