Manufacturing Method of Semiconductor Device

• US 20090075433A1
• Filed: 11/14/2008
• Published: 03/19/2009
• Est. Priority Date: 06/11/2003
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Izumisawa, Masaru, Yoshioka, Hironori, Kouzuki, Shigeo, Aida, Satoshi
• Granted Patent: US 7,994,006 B2
• Time in Patent Office: Days
• US Class Current: 438/138
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminal portion side.

Claims

1. :

A manufacturing method of a semiconductor device comprising;

forming a drift layer of a first conductivity on a first main surface of a semiconductor substrate of a first conductivity type, a surface of the drift layer having a first area for a cell portion and a second area for a terminating portion which is positioned on an outer periphery of the first area and alleviates an electric field to maintain a breakdown voltage by extending a depletion layer;

forming a first insulating film with a first thickness in the second area on the drift layer, the first insulating film having first and second end portions, the first end portion being located closer to the first area than the second end surface;

forming a second insulating film having a second thickness smaller than the first thickness in the first area on the drift layer;

forming a control electrode on the second insulating film;

forming a first base layer in the first area and a second base layer in the second area by implanting a second conductivity impurity into the drift layer using the control electrode and the first insulating film as a mask and then performing a heat treatment to diffuse the impurity;

selectively forming an impurity diffused layer in a surface layer of the second base layer by implanting a second conductivity impurity into the second base layer and then performing a heat treatment to diffuse the impurity implanted into the second base layer, the impurity diffused layer having first and second opposing end surfaces, the first end surface being located closer to the first area than the second end surface;

selectively forming a source layer of a first conductivity type in a surface layer of the first base layer; and

forming first through third metallic compounds in surface layers of the source layer, of the control electrode and of the impurity diffused layer, respectively, by depositing a metallic material on the source layer, the control electrode and the impurity diffused layer, causing the source layer, the control electrode, the impurity diffused layer to react with the metallic material by a heat treatment, and then selectively removing the metallic material, the third metallic compound having third and fourth opposing end surfaces, the third end surface being located closer to the first area than the fourth end surface, and the fourth end surface being spaced from the second end surface of the impurity diffused region by a distance.

2. :

The manufacturing method of a semiconductor device according to claim 1, further comprising forming a first side wall spacer on an end surface of the first insulating film after forming the impurity diffused layer and before forming the first through third metallic compounds,

wherein the third metallic compound is formed in a self-alignment manner using the first side wall spacer as a mask.

3. :

The manufacturing method of a semiconductor device according to claim 1,

wherein the impurity diffused layer is formed in a self-alignment manner with the first end portion of the first insulating film being used as a mask.

4. :

The manufacturing method of a semiconductor device according to claim 2, wherein forming the first side wall spacer includes forming second side wall spacers on side surfaces of the control electrode, and

the second metallic compound is formed so as to extend onto a top face of the second side wall spacers.

5. :

The manufacturing method of a semiconductor device according to claim 1, further comprising forming a third insulating film on the first end portion of the first insulating film,

wherein the second conductivity impurity for the impurity diffused layer is implanted through the third insulating film.

6. :

The manufacturing method of a semiconductor device according to claim 1, wherein the third metallic compound is formed in such a manner that the distance is 0.2 μ

m or more.

7. :

The manufacturing method of a semiconductor device according to claim 1, further comprising forming a field plate electrode on the first insulating film.

8. :

The manufacturing method of a semiconductor device according to claim 7, wherein forming the first through third metallic compounds includes forming a fourth metallic compound in a surface layer of the field plate electrode.

9. :

The manufacturing method of a semiconductor device according to claim 7, wherein the control electrode and the field plate electrode are simultaneously formed.