SIMD DOT PRODUCT OPERATIONS WITH OVERLAPPED OPERANDS

• US 20090077345A1
• Filed: 09/13/2007
• Published: 03/19/2009
• Est. Priority Date: 09/13/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Moyer, William C.
• Granted Patent: US 8,631,224 B2
• Time in Patent Office: Days
• US Class Current: 712/4
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A data processing system includes a plurality of general purpose registers, and processor circuitry for executing one or more instructions, including a vector dot product instruction for simultaneously performing at least two dot products. The vector dot product instruction identifies a first and second source register, each for storing a plurality of vector elements, where a first dot product is to be performed between a first subset of vector elements of the first source register and a first subset of vector elements of the second source register, and a second dot product is to be performed between a second subset of vector elements of the first source register and a second subset of vector elements of the second source register. The first and second subsets of the second source register are different and at least two vector elements of the first and second subsets of the second source register overlap.

Claims

1. A data processing system, comprising:

a plurality of general purpose registers;

processor circuitry for executing one or more instructions, the one or more instructions comprising a vector dot product instruction for simultaneously performing at least two dot products, the vector dot product instruction identifying a first source register from the plurality of general purpose registers, and a second source register from the plurality of general purpose registers, each of the first source register and the second source register for storing a plurality of vector elements, wherein a first dot product of the at least two dot products is to be performed between a first subset of vector elements of the first source register and a first subset of vector elements of the second source register, and a second dot product of the at least two dot products is to be performed between a second subset of vector elements of the first source register and a second subset of vector elements of the second source register, wherein the first and second subsets of the second source register are different and wherein at least two vector elements of the first and second subsets of the second source register overlap.

2. The data processing system of claim 1, wherein the vector dot product instruction further identifies a destination register for storing a result of the first dot product and a result of the second dot product.

3. The data processing system of claim 1, wherein the processor circuitry further comprises an accumulator, and wherein the vector dot product instruction further identifies a destination register for storing a sum of a result of the first dot product and a first value of the accumulator and a sum of a result of the second dot product and a second value of the accumulator.

4. The data processing system of claim 1, wherein the first and second subsets of the first source register are a same subset.

5. The data processing system of claim 1, wherein the first subset of vector elements of the first source register corresponds to same vector element locations as the first subset of vector elements of the second source register.

6. The data processing system of claim 1, wherein the vector dot product instruction further indicates an offset for use in at least indicating which vector elements of the first source register are to be included in the first subset of vector elements of the first source register.

7. The data processing system of claim 6, wherein the vector dot product instruction further indicates a second offset for use in at least indicating which vector elements of the second source register are to be included in the first subset of vector elements of the second source register.

8. The data processing system of claim 1, wherein the vector dot product instruction further indicates an offset for use in at least indicating which vector elements of the second source register are to be included in the first subset of vector elements of the second source register.

9. A data processing system, comprising:

a plurality of general purpose registers; and

processor circuitry for executing one or more instructions, the one or more instructions comprising a vector dot product instruction for simultaneously performing at least two dot products, the vector dot product instruction identifying a first source register from the plurality of general purpose registers, and a second source register from the plurality of general purpose registers, each of the first source register and the second source register for storing a plurality of vector elements, wherein a first dot product of the at least two dot products is to be performed between a first subset of five vector elements of the first source register and a first subset of five vector elements of the second source register, and a second dot product of the at least two dot products is to be performed between a second subset of five vector elements of the first source register and a second subset of five vector elements of the second source register, wherein four vector elements of the first and second subsets of the second source register overlap.

10. The data processing system of claim 9, wherein the vector dot product instruction further identifies a destination register for storing a result of the first dot product and a result of the second dot product.

11. The data processing system of claim 9, wherein the processor circuitry further comprises an accumulator, and wherein the vector dot product instruction further identifies a destination register for storing a sum of a result of the first dot product and a first value of the accumulator and a sum of the a result of the second dot product and a second value of the accumulator.

12. The data processing system of claim 9, wherein the first and second subsets of the first source register are a same subset.

13. The data processing system of claim 9, wherein the first subset of vector elements of the first source register corresponds to same vector element locations as the first subset of vector elements of the second source register.

14. The data processing system of claim 9, wherein each of the first and second source registers identified by the vector dot product instruction is for storing eight vector elements, and wherein the processor circuitry comprises ten multipliers, five of which for performing the first dot product and the other five of which for performing the second dot product.

15. The data processing system of claim 9, wherein the vector dot product instruction further indicates an offset for use in at least indicating which vector elements of the first or second source register are to be included in the first subset of vector elements of the first or second source register.

16. A method for performing simultaneous dot product operations, comprising:

providing a plurality of general purpose registers; and

providing processor circuitry for executing one or more instructions, the one or more instructions comprising a vector dot product instruction for simultaneously performing at least two dot products, the vector dot product instruction identifying a first source register from the plurality of general purpose registers, and a second source register from the plurality of general purpose registers, each of the first source register and the second source register for storing a plurality of vector elements, wherein a first dot product of the at least two dot products is to be performed between a first subset of vector elements of the first source register and a first subset of vector elements of the second source register, and a second dot product of the at least two dot products is to be performed between a second subset of vector elements of the first source register and a second subset of vector elements of the second source register, wherein the first and second subsets of the second source register are different and wherein at least two vector elements of the first and second subsets of the second source register overlap.

17. The method of claim 16, wherein the vector dot product instruction further identifies a destination register for storing a result of the first dot product and a result of the second dot product.

18. The method of claim 16, wherein the processor circuitry further comprises an accumulator, and wherein the vector dot product instruction further identifies a destination register for storing a sum of a result of the first dot product and a first value of the accumulator and a sum of the a result of the second dot product and a second value of the accumulator.

19. The method of claim 16, wherein the first and second subsets of the first source register are a same subset.

20. The method of claim 16, wherein the vector dot product instruction further indicates an offset for use in at least indicating which vector elements of the first or second source register are to be included in the first subset of vector elements of the first or second source register.