MEMORY DEVICE AND SYSTEM WITH BOOTLOADING OPERATION

• US 20090077423A1
• Filed: 09/11/2008
• Published: 03/19/2009
• Est. Priority Date: 09/19/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Chang-Rae, ZHANG, Pyung-Moon
• Granted Patent: US 7,975,178 B2
• Time in Patent Office: Days
• US Class Current: 714/36
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1417 Boot up procedures
• CPC Class Codes: G06F 11/2284 by power-on test, e.g. power-on self test [POST]

Abstract

Provided are a semiconductor memory device, memory system and method of executing a bootloading operation. The method includes cyclically executing a bootloading operation cycle that includes loading the boot information from the memory to the controller, and performing an ECC operation on the boot information. The ECC operation provides a fail condition indication or a pass condition indication and if the fail condition indication is provided, the next bootloading operation cycle is executed.

Claims

1. A semiconductor memory device comprising:

a memory configured to store boot information; and

a controller comprising an error detection and/or correction (ECC) circuit and being configured to execute a bootloading operation, wherein the bootloading operation comprises at least one bootloading operation cycle, and each bootloading operation cycle comprises loading the boot information from the memory and thereafter performing an ECC operation in the ECC circuit in relation to the loaded boot information,

wherein the controller is further configured to execute a next bootloading operation cycle if the ECC operation indicates a fail condition for the loaded boot information.

2. The semiconductor memory device of claim 1, wherein execution of the bootloading operation occurs as a power supply voltage applied to the semiconductor memory device is being brought up to a defined level.

3. The semiconductor memory device of claim 1, wherein the memory is a flash memory.

4. The semiconductor memory device of claim 3, wherein the flash memory and the controller are integrated into one single integrated circuit chip.

5. The semiconductor memory device of claim 1, further comprising:

a delay circuit defining a bootloading operation delay period, wherein the memory controller is further configured to begin execution of the bootloading operation following the bootloading operation delay period.

6. The semiconductor memory device of claim 5, wherein the delay circuit is an oscillator.

7. The semiconductor memory device of claim 6, wherein the bootloading delay period is defined in relation to a power-up indication associated with application of the power supply voltage.

8. The semiconductor memory device of claim 7, further comprising:

a power-on-reset circuit generating the power-up indication after receiving the power supply voltage.

9. The semiconductor memory device of claim 1, further comprising:

a boot RAM storing the loaded boot information.

10. A method of executing a bootloading operation in a memory system including a semiconductor memory device, the semiconductor memory device including a memory storing boot information and a controller comprising an error detection and/or correction (ECC) circuit, the method comprising:

executing a bootloading operation cycle, wherein the bootloading operation cycle comprises;

loading the boot information from the memory to the controller;

performing an ECC operation on the boot information using the ECC circuit; and

providing a fail condition indication or a pass condition indication in relation to the ECC operation; and

if the fail condition indication is provided, executing a next bootloading operation cycle.

11. The method of claim 10, wherein if the pass condition is provided, terminating the bootloading operation.

12. The method of claim 11, further comprising:

after terminating the bootloading operation, performing a boot operation for the memory system.

13. The method of claim 10, further comprising delaying the loading of the boot code for a predetermined delay time.

14. The method of claim 10, further comprising:

receiving a power-up indication; and

delaying execution of a first bootloading operation cycle until a bootloading operation delay period has lapsed.

15. The method of claim 10, wherein the memory is a flash memory and the memory system is integrated onto a single integrated circuit chip.

18. The memory system of claim 15, wherein the flash memory and the controller are integrated into a single integrated circuit chip.

19. The memory system of claim 15, further comprising:

a boot RAM storing the loaded boot information.

16. A memory system comprising:

a flash memory configured to store boot information; and

a controller comprising an error detection and/or correction (ECC) circuit and being configured to execute a bootloading operation, wherein the bootloading operation comprises at least one bootloading operation cycle, and each bootloading operation cycle comprises loading the boot information from the memory and thereafter performing an ECC operation in the ECC circuit in relation to the loaded boot information, wherein the controller is further configured to execute a next bootloading operation cycle if the ECC operation indicates a fail condition for the loaded boot information and terminate the bootloading operation if the ECC operation indicates a pass condition for the loaded boot information; and

a central processing unit (CPU) performing a boot operation once the ECC operation indicates a pass condition for the loaded boot information.

17. The memory system of claim 16, wherein execution of the bootloading operation occurs as a power supply voltage applied to the memory system is being brought up to a defined level.