SIGNAL SEGMENTATION METHOD AND CRC ATTACHMENT METHOD FOR REDUCING UNDETECTED ERROR

• US 20090077446A1
• Filed: 09/08/2008
• Published: 03/19/2009
• Est. Priority Date: 09/08/2007
• Status: Active Grant

• Current Assignee: LG Electronics, Inc. (LG Corporation)
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Kim, Ki Jun, Kim, Bong Hoe, Yun, Young Woo, Lee, Dae Won, Roh, Dong Wook, Seo, Dongyoun, Yu, Nam Yul
• Granted Patent: US 7,793,194 B2
• Time in Patent Office: Days
• US Class Current: 714/755
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/093 CRC update after modification of the information word
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0042 Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape H04L1/0067 takes precedence
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 1/0078 Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location forward error control, e.g. FEC, CRC H04L1/004; adaptive formatting H04L1/0006; mappings H04L27/00

Abstract

The present invention provides for applying a cyclic redundancy check (CRC) to a data signal. The present invention includes attaching a first CRC to a first data signal block having a first length, segmenting the first data signal block attached with the first CRC into a plurality of second data signal blocks having a length shorter than the first length, respectively generating a second CRC for each second data signal block, and attaching the generated second CRC to the respective second data signal block. Moreover, the first CRC and second CRC may be generated from respectively different CRC generating polynomial equations.

Claims

1. A method for applying a cyclic redundancy check (CRC) to a data signal, the method comprising:

attaching a first CRC to a first data signal block having a first length;

segmenting the first data signal block attached with the first CRC into a plurality of second data signal blocks having a length shorter than the first length;

respectively generating a second CRC for each second data signal block; and

attaching the generated second CRC to the respective second data signal block,

wherein the first CRC and second CRC are generated from respectively different CRC generating polynomial equations.

2. The method of claim 1, wherein the first data signal block is a transport block and the second data signal block is a code block.

3. The method of claim 1, wherein the first CRC and the second CRC have a 24-bit length.

4. The method of claim 1, wherein the CRC generating polynomial equations respectively generating the first CRC and second CRC are 24th order polynomial equations.

5. The method of claim 1, wherein the CRC generating polynomial equations respectively generating the first CRC and second CRC satisfy a reciprocal polynomial relation with each other.

6. A system for applying a cyclic redundancy check (CRC) to a data signal, the system comprising:

a processor attaching a first CRC to a first data signal block having a first length, segmenting the first data signal block attached with the first CRC into a plurality of second data signal blocks having a length shorter than the first length, respectively generating a second CRC for each second data signal block, and attaching the generated second CRC to the respective second data signal block,

wherein the processor generates the first CRC and second CRC from respectively different CRC generating polynomial equations.

7. The system of claim 6, wherein the first data signal block is a transport block and the second data signal block is a code block.

8. The system of claim 6, wherein the first CRC and the second CRC have a 24-bit length.

9. The system of claim 6, wherein the CRC generating polynomial equations respectively generating the first CRC and second CRC are 24th order polynomial equations.

10. The system of claim 6, wherein the CRC generating polynomial equations respectively generating the first CRC and second CRC satisfy a reciprocal polynomial relation with each other.

11. A method for applying a cyclic redundancy check (CRC) to a data signal, the method comprising:

attaching a first CRC to a first data signal block having a first length;

segmenting the first data signal block attached with the first CRC into a plurality of second data signal blocks having a length shorter than the first length, wherein the first CRC is attached to one of the plurality of second data signal blocks;

respectively generating a second CRC for each second data signal block; and

attaching the generated second CRC to the respective second data signal block such that one of the plurality of second data signal blocks has an attached first CRC and second CRC,

wherein the first CRC and second CRC are generated from respectively different CRC generating polynomial equations.

12. The method of claim 11, wherein the first data signal block is a transport block and the second data signal block is a code block.

13. The method of claim 11, wherein the first CRC and the second CRC have a 24-bit length.

14. The method of claim 11, wherein the CRC generating polynomial equations respectively generating the first CRC and second CRC are 24th order polynomial equations.

15. The method of claim 11, wherein the CRC generating polynomial equations respectively generating the first CRC and second CRC satisfy a reciprocal polynomial relation with each other.