VERTICALLY TAPERED TRANSMISSION LINE FOR OPTIMAL SIGNAL TRANSITION IN HIGH-SPEED MULTI-LAYER BALL GRID ARRAY PACKAGES

• US 20090077523A1
• Filed: 09/19/2007
• Published: 03/19/2009
• Est. Priority Date: 09/19/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Shi, Hong, Jiang, Xiaohong
• Granted Patent: US 7,752,587 B2
• Time in Patent Office: Days
• US Class Current: 716/130
• CPC Class Codes: G06F 2113/18 Chip packaging
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/0251 related to vias or transitions between vias and transmission lines
• CPC Class Codes: H05K 2201/09627 Special connections between adjacent vias, not for grounding vias
• CPC Class Codes: H05K 2201/09709 Staggered pads, lands or terminals; Parallel conductors in different planes
• CPC Class Codes: H05K 3/0005 for designing circuits by computer
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

Broadly speaking, the embodiments of the present invention fill the need for methods of designing vertical transmission lines for optimal signal transition in multi-layer BGA packages. By controlling the impedance and geometry continuity of micro vias in each micro via layer in the package to follow smooth impedance and geometry curves from layer to layer, the return loss and insertion loss of the transmission line can be reduced or controlled to within acceptable ranges.

Claims

1. A method for designing placement locations of micro vias of a via layer of a transmission line in a multi-layer ball grid array (BGA) package for a semiconductor die, comprising:

determining a target impedance value for the via layer, wherein the determined target impedance value for the layer is along a smooth impedance curve between an impedance of a bump and an impedance of a ball of a BGA;

determining placement location of at least one signal via of micro vias, wherein the placement location follows design constraints of manufacturing;

performing an analytical calculation to determine initial placement locations of a plurality of ground vias of the micro vias of the via layer;

adjusting the placement locations of the plurality of ground vias by taking the design constraints of manufacturing into consideration; and

calculating an impedance of the via layer by using a simulation tool after the placement locations of the vias have been adjusted.

2. The method of claim 1, further comprising:

determining if the calculated impedance of the via layer meets the target impedance value,

if the calculated impedance of the via layer meets the target impedance value, the placement locations of the signal and ground vias of the via layer are accepted,

if the calculated impedance of the via layer does not meet the target impedance value, the placement locations of the ground vias are adjusted and the impedance of the via layer is recalculated, the determining operation being repeated until the calculated impedance of the via layer meets the target impedance value.

3. The method of claim 1, wherein the determining placement location of at least one signal via of micro vias includes placing the at least one signal via to follow a smooth geometry transition in the transmission line.

4. The method of claim 1, wherein the target impedance is determined by one of linear interpolation between the impedance of the bump and the impedance of the ball of the ball grid array or graphical interpolation along the smooth impedance curve between the impedance of the bump and the impedance of the ball of the ball grid array.

5. The method of claim 1, wherein the bump, the micro vias of the via layer, a plated through hole (PTH), and the ball are part of the transmission line.

6. The method of claim 3, wherein placing the at least one signal via to follow the smooth geometry transition is performed by placing the at least one signal via along a smooth curve going through a center of a PTH and an outer edge of the ball of the BGA.

7. The method of claim 6, wherein both the smooth impedance curve and the smooth curve lack sharp transitions in the curves.

8. The method of claim 3, wherein placing the at least one signal via to follow smooth geometry transition to avoid geometry discontinuities of signal vias of multiple via layers of the multi-layer BGA package reduces return loss and insertion loss of the transmission line at high operating frequency range.

9. The method of claim 3, wherein placing the at least one signal via to follow smooth geometry transition to avoid geometry discontinuities of signal vias of multiple via layers of the multi-layer BGA package widens an operating frequency range of devices in the semiconductor die.

10. A method for designing placement locations of micro vias of a via layer of a transmission line in a package for a semiconductor die to widen a range of operating frequencies of devices in the semiconductor die, comprising:

determining a target impedance value for the via layer, wherein the determined target impedance value for the layer is along a smooth impedance curve between an impedance of a bump and an impedance of a ball of a ball grid array (BGA);

determining placement location of at least one signal via of micro vias, wherein the placement location avoids geometry discontinuities in the transmission line;

calculating a distance between ground vias of the micro vias of the via layer and the at least one signal vias to determine initial placement locations of the ground vias; and

calculating an impedance of the via layer by using a simulation tool after the placement locations of the vias have been adjusted.

11. The method of claim 10, further comprising:

determining if the calculated impedance of the via layer meets the target impedance value,

if the calculated impedance of the via layer meets the target impedance value, the placement locations of the signal and ground vias of the via layer are accepted,

if the calculated impedance of the via layer does not meet the target impedance value, the placement locations of the ground vias are adjusted and the impedance of the via layer is recalculated, the determining operation being repeated until the calculated impedance of the via layer meets the target impedance value.

12. The method of claim 10, wherein the target impedance is determined by one of linear interpolation between the impedance of the bump and the impedance of the ball of the ball grid array or graphical interpolation along the smooth impedance curve between the impedance of the bump and the impedance of the ball of the ball grid array.

13. The method of claim 10, wherein the placement locations at least one signal via and the ground vias follow design constraints of manufacturing.

14. The method of claim 10, wherein adjusting placement locations of vias to follow the smooth geometry transition is performed by placing the at least one signal via along a smooth curve between an outer edge of the bump and an outer edge of the ball of the BGA.

15. The method of claim 10, wherein determining placement location of at least one signal via to follow a smooth geometry transition to avoid geometry discontinuity in the transmission line reduces return loss and insertion loss of the transmission line over a frequency range between about 0 GHz to about 15 GHz.

16. The method of claim 10, wherein placing the at least one signal via to follow smooth geometry transition to avoid geometry discontinuity of signal vias of multiple via layers of the multi-layer BGA package reduces return loss and insertion loss of the transmission line and widens the operating frequency range of the devices.

20. The computer readable medium of claim 10, wherein placing the at least one signal via to follow smooth geometry transition to avoid geometry discontinuity of signal vias of multiple via layers of the multi-layer BGA package reduces return loss and insertion loss of the transmission line and widens the operating frequency range of the devices.

17. A computer readable medium including program instructions for designing placement locations of micro vias of a via layer of a transmission line in a package for a semiconductor die to widen a range of operating frequencies of devices in the semiconductor die, comprising:

program instructions for determining a target impedance value for the via layer, wherein the determined target impedance value for the layer is along a smooth impedance curve between an impedance of a bump and an impedance of a ball of a ball grid array (BGA);

program instructions for determining placement location of at least one signal via of micro vias, wherein the placement location avoids geometry discontinuities in the transmission line;

program instructions for calculating a distance between ground vias of the micro vias of the via layer and the at least one signal vias to determine initial placement locations of the ground vias; and

program instructions for calculating an impedance of the via layer after the placement locations of the vias have been adjusted.

18. The computer readable medium of claim 17, further comprising:

program instructions for determining if the calculated impedance of the via layer meets the target impedance value,

if the calculated impedance of the via layer meets the target impedance value, the placement locations of the signal and ground vias of the via layer are accepted,

if the calculated impedance of the via layer does not meet the target impedance value, the placement locations of the ground vias are adjusted and the impedance of the via layer is recalculated, the determining operation being repeated until the calculated impedance of the via layer meets the target impedance value.

19. The computer readable medium of claim 17, wherein the target impedance is determined by one of linear interpolation between the impedance of the bump and the impedance of the ball of the ball grid array or graphical interpolation along the smooth impedance curve between the impedance of the bump and the impedance of the ball of the ball grid array.