SEMICONDUCTOR DEVICE

• US 20090079000A1
• Filed: 09/12/2008
• Published: 03/26/2009
• Est. Priority Date: 09/21/2007
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: GODO, Hiromichi, ISOBE, Atsuo, YAMAZAKI, Shunpei, OKAZAKI, Yutaka
• Granted Patent: US 8,044,464 B2
• Time in Patent Office: Days
• US Class Current: 257/351
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/433 Auxiliary members in containers characterised by their shape, e.g. pistons
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]

Abstract

An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.

Claims

1. A semiconductor device comprising:

a substrate having an insulating surface;

a first transistor having a first semiconductor layer, a first gate insulating layer and a first gate electrode layer, over the substrate having the insulating surface;

a first insulating film which covers the first transistor;

an interlayer insulating layer over the first insulating film;

a second transistor having a second semiconductor layer, a second gate insulating layer and a second gate electrode layer, over the interlayer insulating layer; and

a second insulating film which covers the second transistor,

wherein the first semiconductor layer is bonded to the substrate having the insulating surface with a first insulating layer,

wherein the second semiconductor layer is bonded to the interlayer insulating layer with a second insulating layer,

wherein the conductivity type of the first transistor is an n-type and the conductivity type of the second transistor is a p-type, and

wherein the second insulating film has a compressive stress, and a channel formation region of the second semiconductor layer is distorted due to the compressive stress of the second insulating film.

2. The semiconductor device according to claim 1,

wherein the first semiconductor layer and the second semiconductor layer are overlapped with each other with the interlayer insulating layer interposed therebetween, and the first transistor and the second transistor are electrically connected to each other by a wiring which is formed in an opening which penetrates the second insulating film, the second gate insulating layer, the second semiconductor layer, the interlayer insulating layer, the first insulating film, and the first gate insulating layer and reaches the first semiconductor layer.

3. The semiconductor device according to claim 1,

wherein crystal plane orientations of surfaces of the first semiconductor layer and the second semiconductor layer, which are parallel to the insulating surface, are {110}.

4. The semiconductor device according to claim 3,

wherein crystal axes of a channel length direction of the first semiconductor layer and the second semiconductor layer are <

110>

.

5. The semiconductor device according to claim 1,

wherein a channel formation region of the first semiconductor layer is distorted due to a stress of the first insulating film.

6. The semiconductor device according to claim 1,

wherein the first insulating film and the second insulating film are silicon nitride films or silicon nitride oxide films.

7. The semiconductor device according to claim 1,

wherein the interlayer insulating layer is a silicon oxide film or a silicon oxynitride film.

8. The semiconductor device according to claim 1,

wherein the first insulating layer and the second insulating layer are silicon oxide films which are formed by a chemical vapor deposition method using an organosilane gas.

9. The semiconductor device according to claim 1,

wherein the substrate is a glass substrate.

10. The semiconductor device according to claim 1,

wherein each of the first semiconductor film and the second semiconductor film is a single-crystal semiconductor layer.

11. The semiconductor device according to claim 1,

wherein difference in mobility between the first transistor and the second transistor is reduced by causing a distortion in the channel length direction of the second semiconductor layer of the second transistor.

12. A semiconductor device comprising:

a substrate having an insulating surface;

a first transistor having a first semiconductor layer, a first gate insulating layer and a first gate electrode layer, over the substrate having the insulating surface;

a first insulating film which covers the first transistor;

an interlayer insulating layer over the first insulating film;

a second transistor having a second semiconductor layer, a second gate insulating layer and a second gate electrode layer, over the interlayer insulating layer; and

a second insulating film which covers the second transistor,

wherein the first semiconductor layer is bonded to the substrate having the insulating surface with a first insulating layer,

wherein the second semiconductor layer is bonded to the interlayer insulating layer with a second insulating layer,

wherein the conductivity type of the first transistor is an p-type and the conductivity type of the second transistor is a n-type, and

wherein the first insulating film has a compressive stress, and a channel formation region of the first semiconductor layer is distorted due to the compressive stress of the first insulating film.

13. The semiconductor device according to claim 12,

wherein crystal plane orientations of surfaces of the first semiconductor layer and the second semiconductor layer, which are parallel to the insulating surface, are {110}.

14. The semiconductor device according to claim 13,

wherein crystal axes of a channel length direction of the first semiconductor layer and the second semiconductor layer are <

110>

.

15. The semiconductor device according to claim 12,

wherein a channel formation region of the second semiconductor layer is distorted due to a stress of the second insulating film.

16. The semiconductor device according to claim 12,

wherein the first insulating film and the second insulating film are silicon nitride films or silicon nitride oxide films.

17. The semiconductor device according to claim 12,

wherein the interlayer insulating layer is a silicon oxide film or a silicon oxynitride film.

18. The semiconductor device according to claim 12,

wherein the first insulating layer and the second insulating layer are silicon oxide films which are formed by a chemical vapor deposition method using an organosilane gas.

19. The semiconductor device according to claim 12,

wherein the substrate is a glass substrate.

20. The semiconductor device according to claim 12,

wherein each of the first semiconductor film and the second semiconductor film is a single-crystal semiconductor layer.

21. The semiconductor device according to claim 12,

wherein difference in mobility between the first transistor and the second transistor is reduced by causing a distortion in the channel length direction of the second semiconductor layer of the second transistor.

22. A semiconductor device comprising:

a substrate having an insulating surface;

a first semiconductor layer over the substrate having the insulating surface;

a first gate insulating layer over the first semiconductor layer;

a first gate electrode layer over the first gate insulating layer;

a first insulating film over the first insulating layer and the first gate electrode;

an interlayer insulating layer over the first insulating film;

a second semiconductor layer over the interlayer insulating layer;

a second gate insulating layer over the second semiconductor layer;

a second gate electrode layer over the second gate insulating layer; and

a second insulating film over the second gate insulating layer and the second gate electrode,

wherein the first semiconductor layer is bonded to the substrate having the insulating surface with a first insulating layer,

wherein the second semiconductor layer is bonded to the interlayer insulating layer with a second insulating layer,

wherein the first semiconductor layer comprises n-type impurities and the second semiconductor layer comprises p-type impurities, and

wherein the second insulating film has a compressive stress, and a channel formation region of the second semiconductor layer is distorted due to the compressive stress of the second insulating film.

23. The semiconductor device according to claim 22,

wherein each of the first semiconductor film and the second semiconductor film is a single-crystal semiconductor layer.

24. The semiconductor device according to claim 22,

wherein a first transistor comprises the first gate electrode layer, the first gate insulating layer and the first semiconductor layer,

wherein a second transistor comprises the second gate electrode layer, the second gate insulating layer and the second semiconductor layer, and

wherein difference in mobility between the first transistor and the second transistor is reduced by causing a distortion in the channel length direction of the second semiconductor layer of the second transistor.

25. A semiconductor device comprising:

a substrate having an insulating surface;

a first semiconductor layer over the substrate having the insulating surface;

a first gate insulating layer over the first semiconductor layer;

a first gate electrode layer over the first gate insulating layer;

a first insulating film over the first insulating layer and the first gate electrode;

an interlayer insulating layer over the first insulating film;

a second semiconductor layer over the interlayer insulating layer;

a second gate insulating layer over the second semiconductor layer;

a second gate electrode layer over the second gate insulating layer; and

a second insulating film over the second gate insulating layer and the second gate electrode,

wherein the first semiconductor layer is bonded to the substrate having the insulating surface with a first insulating layer,

wherein the second semiconductor layer is bonded to the interlayer insulating layer with a second insulating layer,

wherein the first semiconductor layer comprises p-type impurities and the second semiconductor layer comprises n-type impurities, and

wherein the first insulating film has a compressive stress, and a channel formation region of the first semiconductor layer is distorted due to the compressive stress of the first insulating film.

26. The semiconductor device according to claim 25,

wherein each of the first semiconductor film and the second semiconductor film is a single-crystal semiconductor layer.

27. The semiconductor device according to claim 25,

wherein a first transistor comprises the first gate electrode layer, the first gate insulating layer and the first semiconductor layer,

wherein a second transistor comprises the second gate electrode layer, the second gate insulating layer and the second semiconductor layer, and

wherein difference in mobility between the first transistor and the second transistor is reduced by causing a distortion in the channel length direction of the second semiconductor layer of the second transistor.