NON-POLAR III-V NITRIDE MATERIAL AND PRODUCTION METHOD

• US 20090079035A1
• Filed: 09/26/2007
• Published: 03/26/2009
• Est. Priority Date: 09/26/2007
• Status: Active Grant

• Current Assignee: Quantum NIL Limited, Quantum NIL Limited Taiwan Branch
• Original Assignee: Wang Nang Wang
• Inventors: Wang, Wang Nang
• Granted Patent: US 8,118,934 B2
• Time in Patent Office: Days
• US Class Current: 257/615
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/0265 Pendeoepitaxy

Abstract

A method for growing flat, low defect density, and strain-free thick non-polar III-V nitride materials and devices on any suitable foreign substrates using a fabricated nano-pores and nano-network compliant layer with an HVPE, MOCVD, and integrated HVPE/MOCVD growth process in a manner that minimum growth will occur in the nano-pores is provided. The method produces nano-networks made of the non-polar III-V nitride material and the substrate used to grow it where the network is continuous along the surface of the template, and where the nano-pores can be of any shape.

Claims

1. A method for growing non-polar III-V nitride materials comprising:

(a) providing a template material comprising at least one layer of non-polar III-V nitride semiconductor material;

(b) creating a mask on top of the template material; and

(c) using the mask to form at least one nano-pore and one nano-network in the template material.

2. The method according to claim 1, further comprising the step of:

(d) growing non-polar III-V nitride semiconductor material onto the nano-pores and nano-networks.

3. The method according to claim 1, wherein the template material semiconductor layer is selected from the group consisting of non-polar p-type doped, n-type doped or undoped III-V nitride compounds.

4. The method according to claim 1, wherein the template material comprises a structure selected from the group consisting of:

a simple layer, multiple layers, a heterostructure, and superlattices of the non-polar III-V nitride compound.

5. The method according to claim 1, wherein the template material semiconductor layer comprises one of non-polar In_xGa_yAl_1-x-yN, where 0≦

x≦

1, 0≦

y≦

1, and 0≦

x+y≦

1.

6. The method according to claim 1, wherein the template non-polar III-V nitride layer is formed by deposition onto a substrate by epitaxial growth methods.

7. The method according to claim 1, wherein the template comprises a substrate comprising a material selected from the group consisting of γ

-sapphire, m-silicon carbide, (100) LiAlO₂, non-polar III-V nitride undoped, n-type, p-type and other suitable materials for non-polar III-V nitride material growth.

8. The method according to claim 1, wherein in step (b), the mask is created using a technique selected from the group consisting of metal annealing, anodic porous atumina, e-Beam Lithography, interferometry, holography, photolithography or a nano-imprint method.

9. The method according to claim 1, wherein the template material comprises a sacrificial Layer of non-polar p-GaN.

10. The method according to claim 1, wherein in step (c), the nano-pores and nano-networks are formed by etching the template material.

11. The method according to claim 10, wherein the etching is used to remove part of the substrate.

12. The method according to claim 10, wherein after etching any remaining metal or dielectric material on the nano-networks and nano-pores is removed.

13. The method according to claim 1, wherein the nano-network is continuous in the template.

14. The method according to claim 1, wherein the nano-pores comprise a shape selected from the group consisting of circular, square, rectangular, triangular, trapezoidal, and other polygons.

15. The method according to claim 1, further comprising the step of subjecting the nano-pores and nano-networks to a nitridation or oxidation process.

16. The method according to claim 1, wherein each nano-network comprises a sacrificial layer that is one of either mechanically weakened or can be selectively etched off by a method selected from the group consisting of wet, photochemical, and electrochemical means.

17. The method according to claim 2, wherein step (d) comprises laterally overgrowing an initial layer of non-polar III-V nitride material and then vertically growing the material or device structure onto the initial layer.

18. A method according to claim 17, wherein the laterally overgrown and vertical grown non-polar III-V nitride material comprises a different material from the nano-network.

19. The method according to claim 2, further comprising forming a semiconductor device structure onto the non-polar III-V nitride material.

20. The method according to claim 2, further comprising bonding the grown non-polar III-V nitride material to a submount with good thermal management properties.

21. The method according to claim 2, further comprising separating the non-polar III-V nitride material from the template by a method selected from the group consisting of rapidly cooling the material, mechanical separation, wet etching, electrochemical etching and laser ablation.

22. The method according to claim 2, further comprising processing the grown non-polar III-V nitride material to a predetermined thickness by at least one method selected from the group consisting of slicing, grinding, lapping and polishing.

23. The method according to claim 1, wherein the template material comprises a non-polar III-V nitride material previously produced by a method comprising:

(a) providing a template material comprising at least one layer of non-polar III-V nitride semiconductor material;

(b) creating a mask on top of the template material; and

(c) using the mask to form at least one nano-pore and one nano-network in the template material; and

(d) growing non-polar III-V nitride semiconductor material onto the nano-pores and nano-networks.

24. A non-polar III-V nitride semiconductor material formed by a method in accordance with claim 1.

25. A non-polar III-V nitride semiconductor material comprising nano-pores, formed by a method in accordance with claim 1.