SEMICONDUCTOR DEVICE INCLUDING ELECTRONIC COMPONENT COUPLED TO A BACKSIDE OF A CHIP

• US 20090079065A1
• Filed: 09/21/2007
• Published: 03/26/2009
• Est. Priority Date: 09/21/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Furgut, Edward, Mahler, Joachim, Bauer, Michael
• Granted Patent: US 8,350,382 B2
• Time in Patent Office: Days
• US Class Current: 257/724
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/051 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor package includes a substrate, at least one chip including a first side and a backside opposite of the first side, the first side electrically coupled to the substrate, a conductive layer coupled to the backside of the at least one chip, and at least one electronic component coupled to the conductive layer and in electrical communication with the substrate.

Claims

1. A semiconductor package comprising:

a substrate;

at least one chip including a first side and a backside opposite of the first side, the first side electrically coupled to the substrate;

a conductive layer coupled to the backside of the at least one chip; and

at least one electronic component coupled to the conductive layer and in electrical communication with the substrate.

2. The semiconductor package of claim 1, wherein the first side of at least one chip is an active side, the chip defining vias extending between the active side and the backside, the active side flip chip bonded to the substrate by bumps, and the at least one electronic component electrically communicating with the substrate through the vias and the bumps.

3. The semiconductor package of claim 1, wherein the substrate comprises a redistribution layer and the at least one chip comprises an embedded chip electrically coupled to the redistribution layer, the chip defining vias extending between the first side and the backside, and the at least one electronic component electrically communicating with the redistribution layer through the vias.

4. The semiconductor package of claim 1, wherein the at least one electronic component comprises a passive electrical component selected from the group consisting of a resistor, an inductor, and a capacitor.

5. The semiconductor package of claim 1, wherein the at least one electronic component comprises an active electrical component.

6. The semiconductor package of claim 1, wherein the conductive layer comprises a metallization layer deposited over less than an entirety of the backside of the at least one chip.

7. The semiconductor package of claim 1, wherein the conductive layer comprises a plate defining a through-hole structure and a metal layer deposited over a portion of the plate and in a portion of the through-holes.

8. The semiconductor package of claim 7, wherein the chip comprises at least one via formed between the first side and the backside, the metal layer defining an electrical path extending from the electronic component to the substrate through the plate and through the via in the chip.

9. The semiconductor package of claim 7, wherein the metal layer comprises copper and the at least one electronic component is direct copper bonded to the plate.

10. A semiconductor package comprising:

a carrier defining a first surface and a second surface;

at least one chip coupled to the carrier, the at least one chip including a first face, a second face opposite of the first face, first and second vias formed in the chip between the first and second faces, the first face electrically coupled to the carrier;

a bond layer coupled to the second face of the chip, the bond layer in electrical communication with the carrier through at least one of the first and second vias formed in the chip;

at least one electronic component coupled to the bond layer; and

encapsulation material deposited on the chip and the first surface of the carrier.

11. The semiconductor package of claim 10, wherein the bond layer comprises a metallization layer deposited on a portion of the second face of the chip.

12. The semiconductor package of claim 10, wherein the bond layer comprises a plate defining a through-hole structure and a metal layer deposited over a portion of the plate and in a portion of the through-holes, the plate coupled to the second face of the chip.

13. The semiconductor package of claim 12, wherein the at least one chip comprises metal bumps deposited on the first face, the metal bumps electrically coupled to the first surface of the carrier.

14. The semiconductor package of claim 12, wherein the carrier comprises a thin film including an electrical interconnect and the at least one chip is electrically coupled to the electrical interconnect.

15. An electronic device comprising:

a substrate;

at least one chip including a first side and a backside opposite of the first side, the first side electrically coupled to the substrate; and

means for electrically coupling at least one electronic component to the backside of the chip such that the electronic component is in electrical communication with the substrate.

16. The semiconductor device of claim 15, wherein the means for electrically coupling at least one electronic component to the backside of the chip comprises a metallization layer deposited on the chip between the backside of the chip and the electronic component, the metallization layer comprising a multi-layer structure including a diffusion barrier layer.

17. The semiconductor device of claim 15, wherein the means for electrically coupling at least one electronic component to the backside of the chip comprises a through-hole plate coupled to the backside of the chip and an electrically conductive bond layer deposited between the through-hole structure and the electronic component.

18. A method of fabricating a semiconductor package to include vertically stacked components, the method comprising:

providing a substrate;

providing at least one chip including a first side and a backside opposite of the first side, the first side coupled to the substrate; and

coupling at least one electronic component to the backside of the chip that is in electrical communication with the carrier.

19. The method of claim 18, wherein providing at least one chip comprises providing at least one chip defining vias extending between the first side and the backside, the at least one chip flip chip coupled to the substrate by metal bumps.

20. The method of claim 18, wherein providing at least one chip comprises providing at least one chip defining vias extending between the first side and the backside and embedding the at least one chip flip chip into a carrier substrate.

21. The method of claim 18, wherein coupling at least one electronic component to the backside of the chip comprises coupling at least one of a passive electrical component and an active component to the backside of the chip by a metallization layer.

22. The method of claim 18, wherein coupling at least one electronic component to the backside of the chip comprises:

coupling at least one electronic component to a plate;

function testing all electronic components coupled to the plate; and

coupling the plate to the backside of the chip.

23. A method of fabricating a semiconductor package to include vertically stacked components, the method comprising:

providing a substrate;

providing at least one chip electrically coupled to the substrate;

electrically coupling at least one electronic component to a plate;

function testing all electronic components coupled to the plate; and

coupling the plate to an exposed backside of the chip.

24. The method of claim 23, wherein electrically coupling at least one electronic component to a plate comprises electrically coupling at least one passive electrical component to a plate.

25. The method of claim 23, wherein electrically coupling at least one electronic component to a plate comprises electrically coupling at least one semiconductor chip to a plate.