POWER DEVICE AND STORAGE APPARATUS

• US 20090079264A1
• Filed: 09/17/2008
• Published: 03/26/2009
• Est. Priority Date: 09/21/2007
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Minami, Akira
• Application Number:
  US12/212,164
• Publication Number:
  US 20090079264A1
• Time in Patent Office: Days
• US Class Current: 307/44
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips

Abstract

One aspect of the embodiments utilizes a power adapter includes a main USB connector, an assist USB connector, a drive USB connector, and a power supply current combining circuit that combines a current from a power supply terminal of the main USB connector and a current from a power supply terminal of the assist USB connector so as to output a combined current to a power supply terminal of the drive USB connector. The adapter mutually inputs/outputs signals between the signal terminals of the main USB connector and the signal terminals of the drive USB connector.

Claims

1. A power adapter to connect a host apparatus to an external storage apparatus through USB cables via connectors, the power adapter comprising:

a main USB connector that includes a power supply terminal, a ground terminal, and a pair of signal terminals and that is externally connected to a main USB cable extending from the host apparatus;

an assist USB connector that includes a power supply terminal, a ground terminal, and a pair of signal terminals and that is externally connected to an assist USB cable extending from the host apparatus;

a drive USB connector that includes a power supply terminal, a ground terminal, and a pair of signal terminals and that is externally connected to a USB cable extending from the storage apparatus; and

a power supply current combining circuit that combines a current from the power supply terminal of the main USB connector and a current from the power supply terminal of the assist USB connector so as to output a combined current to the power supply terminal of the drive USB connector and that mutually inputs/outputs signals between the signal terminals of the main USB connector and the signal terminals of the drive USB connector.

2. The power adapter according to claim 1, wherein the main USB connector and the assist USB connector are B-type USB female connectors or mini-B-type USB female connectors, and wherein the drive USB connector is an A-type USB connector.

3. The power adapter according to claim 1, wherein the main USB connector and the assist USB connector are B-type USB female connectors or mini-B-type USB female connectors, and wherein the drive USB connector is a B-type USB female connector or a mini-B-type USB female connector connected to a USB cable extending from the inside of the adapter to the outside.

4. The power adapter according to claim 1, wherein, in the power supply current combining circuit, a power supply line and a ground line extending from the main USB connector connect to a power supply line and a ground line extending from the assist USB connector, respectively, so as to be combined into common lines which connect to the drive USB connector.

5. The power adapter according to claim 4, wherein, in the power supply current combining circuit, the power supply line extending from the main USB connector and the power supply line extending from the assist USB connector connect to each other via reverse-current-preventing diodes so as to be combined into a common line which connects to the drive USB connector.

6. The power adapter according to claim 4, wherein the power supply current combining circuit comprises:

a first MOS-FET provided in the power supply line extending from the main USB connector;

a second MOS-FET provided in the power supply line extending from the assist USB connector;

an output power supply line that connects output sides of the first and second MOS-FETs in common and that connects to a load;

a first operational amplifier that receives an input-side voltage and an output-side voltage to the first MOS-FET, that performs control to turn on the first MOS-FET so as to supply power to the load when the input-side voltage is the same as or higher than the output-side voltage, and that performs control to turn off the first MOS-FET so as to prevent a reverse current to the input side when the input-side voltage is lower than the output-side voltage;

a second operational amplifier that receives an input-side voltage and an output-side voltage to the second MOS-FET, that performs control to turn on the second MOS-FET so as to supply power to the load when the input-side voltage is the same as or higher than the output-side voltage, and that performs control to turn off the second MOS-FET so as to prevent a reverse current to the input side when the input-side voltage is lower than the output-side voltage; and

a booster circuit that boosts a power supply voltage supplied through the power supply line extending from the main USB connector or the assist USB connector and that supplies the boosted power supply voltage to the first and second operational amplifiers.

7. The power adapter according to claim 6,

wherein the first and second MOS-FETs are N-channel MOS-FETs and have sources connected to a power input side and drains connected to a power output side,

wherein the output power supply line connects the drains of the first and second N-channel MOS-FETs in common and connects to the load,

wherein the first operational amplifier has a noninverting input terminal connected to the source of the first N-channel MOS-FET and an inverting input terminal connected to the drain of the first N-channel MOS-FET, performs control to turn on the first N-channel MOS-FET so as to supply power to the load when an input-side source voltage is the same as or higher than an output-side drain voltage, and performs control to turn off the first N-channel MOS-FET so as to prevent a reverse current to the input side when the input-side source voltage is lower than the output-side drain voltage, and

wherein the second operational amplifier has a noninverting input terminal connected to the source of the second N-channel MOS-FET and an inverting input terminal connected to the drain of the second N-channel MOS-FET, performs control to turn on the second N-channel MOS-FET so as to supply power to the load when an input-side source voltage is the same as or higher than an output-side drain voltage, and performs control to turn off the second N-channel MOS-FET so as to prevent a reverse current to the input side when the input-side source voltage is lower than the output-side drain voltage.

8. The power adapter according to claim 6,

wherein the first and second MOS-FETs are P-channel MOS-FETs and have drains connected to a power input side and sources connected to a power output side,

wherein the output power supply line connects the sources of the first and second P-channel MOS-FETs in common and connects to the load,

wherein the first operational amplifier has a noninverting input terminal connected to the source of the first P-channel MOS-FET and an inverting input terminal connected to the drain of the first P-channel MOS-FET, performs control to turn on the first P-channel MOS-FET so as to supply power to the load when an input-side drain voltage is the same as or higher than an output-side source voltage, and performs control to turn off the first P-channel MOS-FET so as to prevent a reverse current to the input side when the input-side drain voltage is lower than the output-side source voltage, and

wherein the second operational amplifier has a noninverting input terminal connected to the source of the second P-channel MOS-FET and an inverting input terminal connected to the drain of the second P-channel MOS-FET, performs control to turn on the second P-channel MOS-FET so as to supply power to the load when an input-side drain voltage is the same as or higher than an output-side source voltage, and performs control to turn off the second P-channel MOS-FET so as to prevent a reverse current to the input side when the input-side drain voltage is lower than the output-side source voltage.

9. A power adapter to connect a host apparatus to an external storage apparatus through USB cables via connectors, the power adapter comprising:

a main USB connector that includes a power supply terminal, a ground terminal, and a pair of signal terminals and that is externally connected to a main USB cable extending from the host apparatus;

an assist USB connector that includes a power supply terminal, a ground terminal, and a pair of signal terminals and that is externally connected to an assist USB cable extending from the host apparatus;

a DC jack that includes a power supply terminal and a ground terminal and that is externally connected to an adapter cable extending from an AC adapter to convert AC power to DC power;

a drive USB connector that includes a power supply terminal, a ground terminal, and a pair of signal terminals and that is externally connected to a USB cable extending from the storage apparatus; and

a power supply current combining circuit that combines a current from the power supply terminal of the main USB connector, a current from the power supply terminal of the assist USB connector, and a current from the power supply terminal of the DC jack so as to output a combined current to the power supply terminal of the drive USB connector and that mutually inputs/outputs signals between the signal terminals of the main USB connector and the signal terminals of the drive USB connector.

10. The power adapter according to claim 9, wherein the main USB connector and the assist USB connector are B-type USB female connectors or mini-B-type USB female connectors, and wherein the drive USB connector is an A-type USB connector.

11. The power adapter according to claim 9, wherein the main USB connector and the assist USB connector are B-type USB female connectors or mini-B-type USB female connectors, and wherein the drive USB connector is a B-type USB female connector or a mini-B-type USB female connector connected to a USB cable extending from the inside of the adapter to the outside.

12. The power adapter according to claim 9, wherein, in the power supply current combining circuit, a power supply line and a ground line extending from the main USB connector, a power supply line and a ground line extending from the assist USB connector, and a power supply line and a ground line extending from the DC jack connect to each other, respectively, so as to be combined into common lines which connect to the drive USB connector.

13. The power adapter according to claim 12, wherein, in the power supply current combining circuit, the power supply line extending from the main USB connector, the power supply line extending from the assist USB connector, and the power supply line extending from the DC jack connect to each other via reverse-current-preventing diodes so as to be combined into a common line which connects to the drive USB connector.

14. The power adapter according to claim 12, wherein the power supply current combining circuit comprises:

a first MOS-FET provided in the power supply line extending from the main USB connector;

a second MOS-FET provided in the power supply line extending from the assist USB connector;

a third MOS-FET provided in the power supply line extending from the DC jack;

an output power supply line that connects output sides of the first, second, and third MOS-FETs in common and that connects to a load;

a first operational amplifier that receives an input-side voltage and an output-side voltage to the first MOS-FET, that performs control to turn on the first MOS-FET so as to supply power to the load when the input-side voltage is the same as or higher than the output-side voltage, and that performs control to turn off the first MOS-FET so as to prevent a reverse current to the input side when the input-side voltage is lower than the output-side voltage;

a second operational amplifier that receives an input-side voltage and an output-side voltage to the second MOS-FET, that performs control to turn on the second MOS-FET so as to supply power to the load when the input-side voltage is the same as or higher than the output-side voltage, and that performs control to turn off the second MOS-FET so as to prevent a reverse current to the input side when the input-side voltage is lower than the output-side voltage;

a third operational amplifier that receives an input-side voltage and an output-side voltage to the third MOS-FET, that performs control to turn on the third MOS-FET so as to supply power to the load when the input-side voltage is the same as or higher than the output-side voltage, and that performs control to turn off the third MOS-FET so as to prevent a reverse current to the input side when the input-side voltage is lower than the output-side voltage; and

a booster circuit that boosts a power supply voltage supplied through the power supply line extending from the main USB connector or the assist USB connector and that supplies the boosted power supply voltage to the first, second, and third operational amplifiers.

15. The power adapter according to claim 14,

wherein the first, second, and third MOS-FETs are N-channel MOS-FETs and have sources connected to a power input side and drains connected to a power output side,

wherein the output power supply line connects the drains of the first, second, and third N-channel MOS-FETs in common and connects to the load,

wherein the first operational amplifier has a noninverting input terminal connected to the source of the first N-channel MOS-FET and an inverting input terminal connected to the drain of the first N-channel MOS-FET, performs control to turn on the first N-channel MOS-FET so as to supply power to the load when an input-side source voltage is the same as or higher than an output-side drain voltage, and performs control to turn off the first N-channel MOS-FET so as to prevent a reverse current to the input side when the input-side source voltage is lower than the output-side drain voltage,

wherein the second operational amplifier has a noninverting input terminal connected to the source of the second N-channel MOS-FET and an inverting input terminal connected to the drain of the second N-channel MOS-FET, performs control to turn on the second N-channel MOS-FET so as to supply power to the load when an input-side source voltage is the same as or higher than an output-side drain voltage, and performs control to turn off the second N-channel MOS-FET so as to prevent a reverse current to the input side when the input-side source voltage is lower than the output-side drain voltage, and

wherein the third operational amplifier has a noninverting input terminal connected to the source of the third N-channel MOS-FET and an inverting input terminal connected to the drain of the third N-channel MOS-FET, performs control to turn on the third N-channel MOS-FET so as to supply power to the load when an input-side source voltage is the same as or higher than an output-side drain voltage, and performs control to turn off the third N-channel MOS-FET so as to prevent a reverse current to the input side when the input-side source voltage is lower than the output-side drain voltage.

16. The power adapter according to claim 14,

wherein the first, second, and third MOS-FETs are P-channel MOS-FETs and have drains connected to a power input side and sources connected to a power output side,

wherein the output power supply line connects the sources of the first, second, and third P-channel MOS-FETs in common and connects to the load,

wherein the first operational amplifier has a noninverting input terminal connected to the source of the first P-channel MOS-FET and an inverting input terminal connected to the drain of the first P-channel MOS-FET, performs control to turn on the first P-channel MOS-FET so as to supply power to the load when an input-side drain voltage is the same as or higher than an output-side source voltage, and performs control to turn off the first P-channel MOS-FET so as to prevent a reverse current to the input side when the input-side drain voltage is lower than the output-side source voltage,

wherein the second operational amplifier has a noninverting input terminal connected to the source of the second P-channel MOS-FET and an inverting input terminal connected to the drain of the second P-channel MOS-FET, performs control to turn on the second P-channel MOS-FET so as to supply power to the load when an input-side drain voltage is the same as or higher than an output-side source voltage, and performs control to turn off the second P-channel MOS-FET so as to prevent a reverse current to the input side when the input-side drain voltage is lower than the output-side source voltage, and

wherein the third operational amplifier has a noninverting input terminal connected to the source of the third P-channel MOS-FET and an inverting input terminal connected to the drain of the third P-channel MOS-FET, performs control to turn on the third P-channel MOS-FET so as to supply power to the load when an input-side drain voltage is the same as or higher than an output-side source voltage, and performs control to turn off the third P-channel MOS-FET so as to prevent a reverse current to the input side when the input-side drain voltage is lower than the output-side source voltage.

17. The power adapter according to claim 14, wherein the booster circuit is a voltage doubler circuit having a switched-capacitor configuration or a booting DC-DC converter.

18. A storage apparatus externally connected to a host apparatus via a USB interface, the storage apparatus comprising:

a first USB connector from which a power supply line, a ground line, and a pair of signal lines extend;

a second USB connector from which only a power supply line and a ground line extend;

a first MOS-FET provided in the power supply line extending from the first USB connector;

a second MOS-FET provided in the power supply line extending from the second USB connector;

an output power supply line that connects output sides of the first and second MOS-FETs in common and that connects to a load;

a first operational amplifier that receives an input-side voltage and an output-side voltage to the first MOS-FET, that performs control to turn on the first MOS-FET so as to supply power to the load when the input-side voltage is the same as or higher than the output-side voltage, and that performs control to turn off the first MOS-FET so as to prevent a reverse current to the input side when the input-side voltage is lower than the output-side voltage;

a second operational amplifier that receives an input-side voltage and an output-side voltage to the second MOS-FET, that performs control to turn on the second MOS-FET so as to supply power to the load when the input-side voltage is the same as or higher than the output-side voltage, and that performs control to turn off the second MOS-FET so as to prevent a reverse current to the input side when the input-side voltage is lower than the output-side voltage; and

a booster circuit that boosts a power supply voltage supplied through the power supply line extending from the first USB connector or the second USB connector and that supplies the boosted power supply voltage to the first and second operational amplifiers.

19. The storage apparatus according to claim 18,

wherein the first and second MOS-FETs are N-channel MOS-FETs and have sources connected to a power input side and drains connected to a power output side,

wherein the output power supply line connects the drains of the first and second N-channel MOS-FETs in common and connects to the load,

wherein the first operational amplifier has a noninverting input terminal connected to the source of the first N-channel MOS-FET and an inverting input terminal connected to the drain of the first N-channel MOS-FET, performs control to turn on the first N-channel MOS-FET so as to supply power to the load when an input-side source voltage is the same as or higher than an output-side drain voltage, and performs control to turn off the first N-channel MOS-FET so as to prevent a reverse current to the input side when the input-side source voltage is lower than the output-side drain voltage, and

wherein the second operational amplifier has a noninverting input terminal connected to the source of the second N-channel MOS-FET and an inverting input terminal connected to the drain of the second N-channel MOS-FET, performs control to turn on the second N-channel MOS-FET so as to supply power to the load when an input-side source voltage is the same as or higher than an output-side drain voltage, and performs control to turn off the second N-channel MOS-FET so as to prevent a reverse current to the input side when the input-side source voltage is lower than the output-side drain voltage.

20. The storage apparatus according to claim 18,

wherein the first and second MOS-FETs are P-channel MOS-FETs and have drains connected to a power input side and sources connected to a power output side,

wherein the output power supply line connects the sources of the first and second P-channel MOS-FETs in common and connects to the load,

wherein the first operational amplifier has a noninverting input terminal connected to the source of the first P-channel MOS-FET and an inverting input terminal connected to the drain of the first P-channel MOS-FET, performs control to turn on the first P-channel MOS-FET so as to supply power to the load when an input-side drain voltage is the same as or higher than an output-side source voltage, and performs control to turn off the first P-channel MOS-FET so as to prevent a reverse current to the input side when the input-side drain voltage is lower than the output-side source voltage, and

wherein the second operational amplifier has a noninverting input terminal connected to the source of the second P-channel MOS-FET and an inverting input terminal connected to the drain of the second P-channel MOS-FET, performs control to turn on the second P-channel MOS-FET so as to supply power to the load when an input-side drain voltage is the same as or higher than an output-side source voltage, and performs control to turn off the second P-channel MOS-FET so as to prevent a reverse current to the input side when the input-side drain voltage is lower than the output-side source voltage.