Systems and methods for cell balancing

• US 20090079391A1
• Filed: 09/25/2007
• Published: 03/26/2009
• Est. Priority Date: 09/25/2007
• Status: Abandoned Application

• Current Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Original Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Inventors: Xiao, Anquen, Sheng, Kaiyi, Bucur, Constantin, Zeng, Xiaojun, Lupu, Flavius
• Application Number:
  US11/903,850
• Publication Number:
  US 20090079391A1
• Time in Patent Office: Days
• US Class Current: 320/122
• CPC Class Codes: H02J 7/0016 using shunting, discharge or bypass circuits

Abstract

A cell balancing circuit comprises a first cell having a first voltage, a second cell in series with the first cell and having a second voltage that is greater than the first voltage, and a bypass path in parallel with the second cell for enabling a bypass current for the second cell if a difference between the first voltage and the second voltage is greater than a predetermined threshold. The bypass current is enabled for a balancing time period that is proportional to the difference between the fist voltage and the second voltage.

Claims

1. A cell balancing circuit comprising:

a first cell having a first voltage;

a second cell in series with said first cell and having a second voltage that is greater than said first voltage; and

a bypass path in parallel with said second cell for enabling a bypass current for said second cell if a difference between said first voltage and said second voltage is greater than a predetermined threshold,

wherein said bypass current flows through said bypass path and is enabled for a balancing time period that is proportional to said difference.

2. The cell balancing circuit as claimed in claim 1, further comprising:

a logic core operable for receiving a first monitoring signal indicative of said first voltage and a second monitoring signal indicative of said second voltage, and for determining said balancing time period.

3. The cell balancing circuit as claimed in claim 1, further comprising:

a balancing controller for conducting said bypass path for said balancing time period, if said difference is greater than said predetermined threshold.

4. The cell balancing circuit as claimed in claim 1, further comprising:

a monitoring circuit operable for monitoring said first voltage and said second voltage.

5. A cell balancing circuit comprising:

a first bypass path in parallel with a first cell operable for enabling a first bypass current for said first cell;

a second bypass path in parallel with a second cell operable for enabling a second bypass current for said second cell coupled in series with said first cell,

wherein said first bypass current and said second bypass current are enabled simultaneously for a predetermined constant period if both said first cell and said second cell meet an unbalanced condition.

6. The cell balancing circuit as claimed in claim 5, wherein said first bypass current flows through said first bypass path, and wherein said second bypass current flows through said second bypass path.

7. The cell balancing circuit as claimed in claim 5, wherein both said first cell and said second cell meet said unbalanced condition if a first voltage of said first cell is greater than a predetermined threshold, and a second voltage of said second cell is greater than said predetermined threshold.

8. The cell balancing circuit as claimed in claim 5, wherein both said first cell and said second cell meet said unbalanced condition if a first difference between a first voltage of said first cell and a third voltage of a third cell is greater than a predetermined threshold, and a second difference between a second voltage of said second cell and said third voltage is greater than said predetermined threshold, and wherein said third cell is in series with said first cell and said second cell.

9. The cell balancing circuit as claimed in claim 5, further comprising:

a monitoring circuit for monitoring a first voltage of said first cell and a second voltage of said second cell.

10. A cell balancing circuit comprising:

a logic core for measuring a first state-of-charge(SOC) indicative of a first charge level of a first cell, and for measuring a second SOC indicative of a second charge level of a second cell that is in series with said first cell, wherein said second SOC is greater than said first SOC; and

a bypass path in parallel with said second cell for enabling a bypass current for said second cell if a difference between said first SOC and said second SOC is greater than a predetermined threshold,

wherein said bypass current is enabled for a balancing time period.

11. The cell balancing circuit as claimed in claim 10, wherein said balancing time period is proportional to said difference.

12. The cell balancing circuit as claimed in claim 10, wherein said balancing time period is equal to a predetermined constant period.

13. The cell balancing circuit as claimed in claim 10, wherein said first SOC is determined by a ratio of a cell capacity of said first cell to a full charge capacity of said first cell.

14. The cell balancing circuit as claimed in claim 10, wherein said second SOC is determined by a ratio of a cell capacity of said second cell to a full charge capacity of said second cell.

15. A method for cell balancing, comprising:

measuring a first state-of-charge(SOC) indicative of a first charge level of a first cell;

measuring a second SOC indicative of a second charge level of a second cell that is in series with said first cell, wherein said second SOC is greater than said first SOC; and

enabling a bypass current for said second cell if a difference between said first SOC and said second SOC is greater than a predetermined threshold,

wherein said bypass current is enabled for a balancing time period.

16. The method as claimed in claim 15, wherein said balancing time period is proportional to said difference.

17. The method as claimed in claim 15, wherein said balancing time period is equal to a predetermined constant period.

18. The method as claimed in claim 15, wherein said first SOC is determined by a ratio of a cell capacity of said first cell to a full charge capacity of said first cell.

19. The method as claimed in claim 15, wherein said second SOC is determined by a ratio of a cell capacity of said second cell to a full charge capacity of said second cell.

20. A cell balancing circuit comprising:

a bypass path in parallel with a cell in a battery pack; and

a charging and balancing controller coupled to said cell and operable for generating a charging termination signal to halt charging power to said battery pack if a cell voltage of said cell reaches a predetermined maximum cell charging voltage, and operable for generating a cell balancing signal to enable a bypass current through said bypass path if said cell voltage reaches a predetermined threshold that is less than said predetermined maximum cell charging voltage.

21. The cell balancing circuit as claimed in claim 20, wherein said charging and balancing controller comprises a first comparator coupled to said cell and operable for comparing said cell voltage with said predetermined maximum cell charging voltage and operable for generating said charging termination signal, and a second comparator coupled to said cell and operable for comparing said cell voltage with said predetermined threshold and operable for generating said cell balancing signal.