METHOD AND APPARATUS FOR UPGRADING FPGA/CPLD FLASH DEVICES

• US 20090079467A1
• Filed: 09/26/2007
• Published: 03/26/2009
• Est. Priority Date: 09/26/2007
• Status: Abandoned Application

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Sandven, Magne V., Sudgarden, Arne, Arntsen, Roy
• Application Number:
  US11/861,830
• Publication Number:
  US 20090079467A1
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/1776 for memories

Abstract

A method for programming a non-volatile memory associated with a programmable logic device (PLD). The method for programming a non-volatile memory includes a reading a data file, wherein the data file includes information to be programmed into the non-volatile memory. The data file is then translated into a plurality of commands based on the information contained therein. The plurality of command is forwarded to a microcontroller. The microcontroller then executes the plurality of commands, wherein said executing causes the non-volatile memory to be programmed.

Claims

1. A method for programming a non-volatile memory associated with a programmable logic device (PLD), the method comprising:

reading a data file, wherein the data file includes information to be programmed into the non-volatile memory;

translating the data file into a plurality of commands based on the information;

forwarding the plurality of commands to a microcontroller; and

executing each of the plurality of commands, wherein said executing causes the non-volatile memory to be programmed, wherein said executing is performed by the microcontroller.

2. The method as recited in claim 1, wherein said reading is performed by a processor, wherein the processor is coupled to the microcontroller by a serial bus.

3. The method as recited in claim 2, wherein the serial bus is a system management bus (SMBus).

4. The method as recited in claim 2, wherein the serial bus is an I²C bus.

5. The method as recited in claim 1, wherein the non-volatile memory is a flash memory.

6. The method as recited in claim 1, wherein the non-volatile memory is a static random access memory (SRAM).

7. The method as recited in claim 1, wherein the data file is a serial vector format (.svf) file.

8. The method as recited in claim 1, wherein the PLD is a field programmable gate array (FPGA).

9. A system comprising:

a processor, wherein the processor is configured to read a data file and translate information in the data file into a plurality of commands;

a microcontroller coupled to receive the plurality of commands from the processor;

a programmable logic device PLD; and

a non-volatile memory associated with the PLD;

wherein the microcontroller is configured to execute each of the plurality of commands, wherein executing the plurality of commands causes the non-volatile memory to be programmed.

10. The system as recited in claim 9, wherein the microcontroller is coupled to the processor by a serial bus.

11. The system as recited in claim 10, wherein the serial bus is a system management bus (SMBus).

12. The system as recited in claim 10, wherein the serial bus is an I²C bus.

13. The system as recited in claim 9, wherein the non-volatile memory is a flash memory.

14. The system as recited in claim 9, wherein the non-volatile memory is a static random access memory (SRAM).

15. The system as recited in claim 9, wherein the data file is a serial vector format (.svf) file.

16. The system as recited in claim 9, wherein the PLD is a field programmable gate array.

17. A method for updating a non-volatile memory associated with a programmable logic device (PLD) in a computing device coupled to a network, the method comprising:

reading a data file on a source computer, wherein the data file includes information to be programmed into the non-volatile memory of each of the one or more computing devices;

translating the data file into a plurality of commands based on information in the data file, wherein said translating is performed by a processor of the source computer;

sending each of the plurality of commands over the network to the computing device, wherein the computing device is remotely located with respect to the source computer; and

executing each of the plurality of commands, wherein said executing causes the non-volatile memory associated with the PLD to be programmed, and wherein said executing is performed by a microcontroller in the computing device.

18. The method as recited in claim 17 further comprising:

sending each of the plurality of commands over the network to a plurality of computing devices, wherein each of the plurality of computing devices is remotely located with respect to the source computer; and

a microcontroller in each of the plurality of computing devices executing each of the plurality of commands, thereby causing a corresponding non-volatile memory associated with a corresponding PLD to be updated.

19. The method as recited in claim 17, wherein the non-volatile memory is a flash memory.

20. The method as recited in claim 17, wherein the PLD is a field programmable gate array (FPGA).