Forming a helical inductor

• US 20090079530A1
• Filed: 09/25/2007
• Published: 03/26/2009
• Est. Priority Date: 09/25/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gurumurthy, Charan, Chickamenahalli, Shamala, Fite, Robert J., Chandrasekhar, Arun, Venkataraman, Srikrishnan, Patel, Priyavadan R.
• Granted Patent: US 7,956,713 B2
• Time in Patent Office: Days
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/165 incorporating printed inductors
• CPC Class Codes: H05K 2201/086 for inductive purposes, e.g. printed inductor with ferrite core
• CPC Class Codes: H05K 2201/0959 Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 2201/09645 Patterning on via walls; Plural lands around one hole
• CPC Class Codes: H05K 3/42 Plated through-holes or plated via connections

Abstract

In one embodiment, the present invention includes an apparatus having a substrate with vias extending between first and second surfaces thereof, and at least one helical inductor adapted within a via, which may be formed of a conductive material. Other embodiments are described and claimed.

Claims

1. An apparatus comprising:

a substrate having a first surface and a second surface, the substrate having a plurality of vias extending between the first surface and the second surface; and

at least one helical inductor adapted within a corresponding one of the plurality of vias, the helical inductor formed of a conductive material and extending between the first surface and the second surface.

2. The apparatus of claim 1, wherein the at least one helical inductor comprises a coupled inductor.

3. The apparatus of claim 2, further comprising a ferrite material coated on an inner wall of the corresponding via, wherein the ferrite material is to contain a magnetic field of the helical inductor.

4. The apparatus of claim 3, wherein the ferrite material is to increase coupling of the helical inductor.

5. The apparatus of claim 1, further comprising a voltage regulator to provide power to a semiconductor die coupled to the substrate, the voltage regulator adapted on the substrate, wherein the helical inductor is coupled to the voltage regulator and the substrate comprises a package substrate.

6. The apparatus of claim 1, further comprising a transformer adapted within the corresponding via, wherein the transformer is formed from a first coil and a second coil, and a ferrite material adapted between the first and second coils, wherein the first coil is wound in an opposite direction to the second coil.

7. The apparatus of claim 1, wherein the at least one helical inductor is part of a compensation circuit to compensate capacitance effects of signal communication.

8. A method comprising:

forming a substrate having a first surface and a second surface, the substrate having a plurality of vias extending between the first surface and the second surface;

forming at least one helical inductor adapted within a corresponding one of the plurality of vias, the helical inductor formed of a conductive material and extending between the first surface and the second surface.

9. The method of claim 8, further comprising forming the helical inductor in a plated through hole (PTH) comprising the corresponding via.

10. The method of claim 9, further comprising coating a ferrite material within the PTH, the ferrite material to shield a magnetic field of the helical inductor.

11. The method of claim 10, further comprising drilling a hole to form the corresponding via, adapting the helical inductor in the via, plugging the via, and adapting a lid plate on the via.

12. The method of claim 8, further comprising corkscrew drilling a hole to form the corresponding via and plating the helical inductor in a corkscrew pattern formed by the corkscrew drilling.

13. The method of claim 12, further comprising adapting a transformer within the corresponding via formed of a first coil and a second coil, the first coil wound in an opposite direction to the second coil, wherein the transformer further includes a ferrite material adapted between the first coil and the second coil.

14. The method of claim 9, further comprising:

adapting a semiconductor die on the substrate, wherein the substrate is a package substrate;

forming a voltage regulator on the package substrate, wherein the voltage regulator is to provide power to the semiconductor die, wherein the helical inductor is part of the voltage regulator.