Generating reference currents compensated for process variation in non-volatile memories

• US 20090080267A1
• Filed: 09/26/2007
• Published: 03/26/2009
• Est. Priority Date: 09/26/2007
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Bedeschi, Ferdinando, Resta, Claudio, Donze, Enzo
• Granted Patent: US 7,675,792 B2
• Time in Patent Office: Days
• US Class Current: 365/189.90
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

In a current reference generator device, a voltage reference generator stage generates a reference voltage (V_ref) and an active element output stage receives the reference voltage (V_ref) and outputs a reference current (I_ref) as a function of the reference voltage (V_ref). A control stage is operatively coupled to the voltage reference generator stage and to the active element output stage and controls a first trimmable parameter (m) associated to the voltage reference generator stage and a second trimmable parameter associated to the active element output stage, so as to compensate for changes in a value of the reference current (I_ref) due to manufacturing process deviations.

Claims

1. A current reference generator comprising:

a voltage reference generator stage to generate a reference voltage;

an active element output stage coupled to receive said reference voltage; and

a control stage operatively coupled to said voltage reference generator stage to control a first trimmable parameter associated with said voltage reference generator stage and a second trimmable parameter associated to said active element output stage to compensate for changes in a value of said reference current due to manufacturing process deviations.

2. The generator according to claim 1, wherein said control stage to receive a control signal and to trim respective values of said first trimmable parameter and of said second trimmable parameter based on said control signal.

3. The generator according to claim 2, wherein said control signal is indicative of a manufacturing process deviation with respect to an ideal manufacturing process.

4. The generator according to claim 3, wherein said active element output stage comprises a MOS transistor arrangement, and said control stage comprises a first trimming block to trim said first trimmable parameter, and a second trimming block to trim said second trimmable parameter, in order to compensate for variations in a threshold voltage and in a gain factor, respectively, of said MOS transistor arrangement due to said manufacturing process deviations.

5. The generator according to claim 4, wherein said first trimming block to trim said first trimmable parameter in order to bias said MOS transistor arrangement in a zero temperature coefficient condition, and said second trimming block to trim said second trimmable parameter in order to set a desired value for said reference current.

6. The generator according to claim 4, wherein said MOS transistor arrangement comprises an array of MOS transistors having different aspect ratios.

7. The generator according to claim 6, wherein said voltage reference generator stage comprises a voltage generator to generate a given voltage, said first trimming block comprising a controllable resistive voltage divider electrically connected to said voltage generator to supply, to a common gate terminal of the MOS transistors of said array, said reference voltage as a partition of said given voltage.

8. The generator according to claim 7, said first trimmable parameter being a partition factor of said controllable resistive voltage divider and said second trimming block comprising a plurality of controllable selector elements connecting a respective MOS transistor of said array to an output terminal of said active element output stage to select at least one MOS transistor of said array to output said reference current at said output terminal, said second trimmable parameter being an aspect ratio of said MOS transistor arrangement.

9. The generator according to claim 8, wherein said control stage to receive a control signal that is in combination of a value of said partition factor and an associated value of said aspect ratio, such that said reference current has reduced variations with said manufacturing process deviations.

10. The generator according to claim 1, said active element output stage including a plurality of selectable transistors with difference aspect ratios.

11. A non-volatile memory comprising:

an array of memory cells; and

a current reference generator device to supply said reference current to said array of memory cells, said generator including;

a voltage reference generator stage to generate a reference voltage;

an active element output stage coupled to receive said reference voltage; and

a control stage operatively coupled to said voltage reference generator stage to control a first trimmable parameter associated with said voltage reference generator stage and a second trimmable parameter associated to said active element output stage to compensate for changes in a value of said reference current due to manufacturing process deviations.

12. The memory according to claim 11, wherein said array of memory cells includes phase change memory cells.

13. The memory according to claim 11, wherein said control stage to receive a control signal and to trim respective values of said first trimmable parameter and of said second trimmable parameter based on said control signal.

14. The memory according to claim 13, wherein said control signal is indicative of a manufacturing process deviation with respect to an ideal manufacturing process.

15. The memory according to claim 14, wherein said active element output stage comprises a MOS transistor arrangement, and said control stage comprises a first trimming block to trim said first trimmable parameter, and a second trimming block to trim said second trimmable parameter, in order to compensate for variations in a threshold voltage and in a gain factor, respectively, of said MOS transistor arrangement due to said manufacturing process deviations.

16. The memory according to claim 15, wherein said first trimming block to trim said first trimmable parameter in order to bias said MOS transistor arrangement in a zero temperature coefficient condition, and said second trimming block to trim said second trimmable parameter in order to set a desired value for said reference current.

17. The memory according to claim 15, wherein said MOS transistor arrangement comprises an array of MOS transistors having different aspect ratios.

18. The memory according to claim 17, wherein said voltage reference generator stage comprises a voltage generator to generate a given voltage, said first trimming block comprising a controllable resistive voltage divider electrically connected to said voltage generator to supply, to a common gate terminal of the MOS transistors of said array, said reference voltage as a partition of said given voltage.

19. The memory according to claim 18, said first trimmable parameter being a partition factor of said controllable resistive voltage divider and said second trimming block comprising a plurality of controllable selector elements connecting a respective MOS transistor of said array to an output terminal of said active element output stage to select at least one MOS transistor of said array to output said reference current at said output terminal, said second trimmable parameter being an aspect ratio of said MOS transistor arrangement.

20. The memory according to claim 19, wherein said control stage to receive a control signal that is in combination of a value of said partition factor and an associated value of said aspect ratio, such that said reference current has reduced variations with said manufacturing process deviations.

21. The memory according to claim 11, said active element output stage including a plurality of selectable transistors with difference aspect ratios.

22. A method comprising:

controlling a first trimmable parameter associated with a voltage reference generator stage and a second trimmable parameter associated with an active element output stage to compensate for changes in a value of said reference current due to manufacturing process deviations.

23. The method according to claim 22, wherein controlling comprises supplying to said current reference generator device a control signal for trimming respective values of said first trimmable parameter and of said second trimmable parameter, said values being related to each other.

24. The method according to claim 23, wherein said trimming respective values of said first and second trimmable parameters comprises compensating for a change in a threshold voltage and in a gain factor, respectively, of a MOS transistor arrangement in said active element output stage due to said manufacturing process deviations.

25. The method according to claim 24, wherein trimming said first trimmable parameter comprises biasing said MOS transistor arrangement in a zero temperature coefficient condition, and trimming said second trimmable parameter comprises setting a desired value for said reference current.

26. The method according to claim 24, wherein trimming comprises selecting at least one MOS transistor of an array of MOS transistors having different aspect ratios to output said reference current.

27. The method according to claim 22, further comprising trimming respective values of said first and second trimmable parameters as a function of a determined deviation from an ideal manufacturing process.

28. The method according to claim 22, further comprising modifying a value of said control signal until said active element output stage supplies a desired value of said reference current.

29. A system comprising:

a processor;

a non-volatile memory coupled to said processor, said memory including an array of memory cells, a current reference generator device to supply said reference current to said array of memory cells, said generator including a voltage reference generator stage to generate a reference voltage, an active element output stage coupled to receive said reference voltage, and a control stage operatively coupled to said voltage reference generator stage to control a first trimmable parameter associated with said voltage reference generator stage and a second trimmable parameter associated to said active element output stage to compensate for changes in a value of said reference current due to manufacturing process deviations; and

a wireless interface coupled to said processor.

30. The system according to claim 29, wherein said cells are phase change memory cells.