Non-Volatile Memory Devices and Methods of Forming the Same

• US 20090081835A1
• Filed: 11/19/2008
• Published: 03/26/2009
• Est. Priority Date: 10/08/2004
• Status: Active Grant

• Current Assignee: Ji-Hoon Park, Sang-Woo Kang, Seong-Gyun Kim, Sung-Woo Park
• Original Assignee: Ji-Hoon Park, Sang-Woo Kang, Seong-Gyun Kim, Sung-Woo Park
• Inventors: Park, Ji-Hoon, Kim, Seong-Gyun, Kang, Sang-Woo, Park, Sung-Woo
• Granted Patent: US 7,723,188 B2
• Time in Patent Office: Days
• US Class Current: 438/157
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate electrode and the fin and includes a first storage gate and a second storage gate. The first storage gate is disposed on a sidewall of the fin, and the second storage gate is disposed on a top surface of the fin and is connected to the first storage gate. A first insulation layer is interposed between the first storage gate and the sidewall of the fin, and a second insulation layer is interposed between the second storage gate and the top surface of the fin. The second insulation layer is thinner than the first insulation layer. A blocking insulation pattern is interposed between the control gate electrode and the floating gate.

Claims

1. A method of forming a non-volatile memory device, comprising:

forming an upwardly protruding fin on a substrate;

sequentially stacking a first insulation layer and a first storage pattern on a sidewall of the fin;

sequentially stacking a second insulation layer and a second storage pattern on a top surface of the fin, the second insulation layer being thinner than the first insulation layer and the second storage pattern being connected to the first storage pattern;

sequentially forming a blocking insulation layer and a control gate conductive layer on the substrate; and

successively patterning the control gate conductive layer, the blocking insulation layer, the first storage pattern, and the second storage pattern to form a floating gate including a first storage gate and a second storage gate, a blocking insulation pattern, and a control gate electrode.

2. The method as recited in claim 1, wherein the first storage gate is made of a first doped polysilicon, and the second storage gate is made of a second doped polysilicon.

3. The method as recited in claim 2, wherein an impurity concentration of the first doped polysilicon is different from that of the second doped polysilicon.

4. The method as recited in claim 3, wherein the impurity concentration of the first doped polysilicon is higher than that of the second doped polysilicon.

5. The method as recited in claim 1, wherein forming the first insulation layer, the first storage pattern, the second insulation layer, and the second storage pattern comprises:

forming a first insulation layer on a top surface and a sidewall of the fin;

forming a first storage layer surrounding the sidewall of the fin on the first insulation layer to expose the first insulation layer formed on the top surface of the fin;

selectively removing the exposed first insulation layer to expose the top surface of the fin;

selectively forming a second insulation layer on the top surface of the exposed fin;

forming a second storage layer to cover the second insulation layer and to be connected to the first storage layer; and

successively patterning the second and first storage layers to form the second and first storage patterns.

6. The method as recited in claim 5, wherein exposing the top surface of the fin and forming the second insulation layer comprise:

forming an oxidation barrier layer on an entire surface of a substrate including the exposed first insulation layer;

patterning the oxidation barrier layer to expose a predetermined region of the exposed first insulation layer;

using the patterned oxidation barrier layer as an etch mask, etching the first insulation layer to expose the top surface of the fin;

thermally oxidizing the substrate to form the second insulation layer; and

removing the patterned oxidation barrier layer.

7. The method as recited in claim 6, wherein at a write or erase operation, the second insulation layer has a thickness sufficient to allow tunneling of charges and the first insulation layer has a thickness sufficient to suppress tunneling of charges.

8. The method as recited in claim 6, wherein an upper corner of the fin is rounded.

9. The method as recited in claim 8, wherein forming the fin comprises:

forming a mask pattern on a predetermined region of a substrate;

thermally oxidizing a substrate including the mask pattern to form a sacrificial thermal oxide layer including a bird'"'"'s beak below the edge of a lower side of the mask pattern;

using the mask pattern as an etch mask, successively anisotropically etching the sacrificial thermal oxide layer and the substrate to form the fin; and

removing the mask pattern and the bird'"'"'s beak, wherein the upper corner of the fin is rounded by the bird'"'"'s beak.

10. The method as recited in claim 5, wherein exposing the top surface of the fin and forming the second insulation layer comprise:

recessing the first storage layer to be shorter than a top surface of the exposed first insulation layer;

forming an oxidation barrier layer on a substrate to fill the recessed region;

planarizing the oxidation barrier layer until the first insulation layer is exposed;

using the planarized oxidation barrier layer as an etch mask, etching the exposed first insulation layer to expose the top surface of the fin;

thermally oxidizing the substrate to form the second insulation layer; and

removing the planarized oxidation barrier layer.

11. The method as recited in claim 10, wherein at a write or erase operation, the second insulation layer has a thickness sufficient to allow tunneling of charges and the first insulation layer has a thickness sufficient to suppress tunneling of charges.

12. The method as recited in claim 10, wherein the upper corner of the fin is rounded.

13. The method as recited in claim 12, wherein forming the fin comprises:

forming a mask pattern on a predetermined region of a substrate;

thermally oxidizing a substrate including the mask pattern to form a sacrificial thermal oxide layer including a bird'"'"'s beak below the edge of a lower side of the mask pattern;

using the mask pattern as an etch mask, successively anisotropically etching the sacrificial thermal oxide layer and the substrate to form the fin; and

removing the mask pattern and the bird'"'"'s beak, wherein the upper corner of the fin is rounded by the bird'"'"'s beak.

14. The method as recited in claim 1, further comprising forming a filling insulation pattern on the substrate to surround a lower sidewall of the fin.

15. The method as recited in claim 1, wherein the substrate is a SOI substrate including a handling substrate, a buried insulation layer, and a device layer which are sequentially stacked and the step of forming the fin includes patterning the device layer to form an upwardly protruding fin on the buried insulation layer.