MESSAGE HANDLER AND METHOD FOR CONTROLLING ACCESS TO DATA OF A MESSAGE MEMORY OF A COMMUNICATIONS MODULE

• US 20090083466A1
• Filed: 06/29/2005
• Published: 03/26/2009
• Est. Priority Date: 08/05/2004
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Hartwich, Florian, Ihle, Markus, Bailer, Franz, Horst, Christian
• Granted Patent: US 8,484,390 B2
• Time in Patent Office: Days
• US Class Current: 710/112
• CPC Class Codes: G06F 13/1663 Access to shared memory

Abstract

A method for controlling access to data of a message memory, and a message handler of a communications module having a message memory, in which data are input or output in response to an access; the message memory being connected to a first buffer configuration and a second buffer configuration, and the data being accessed via the first or the second buffer configuration; in the message handler, at least one first finite state machine being provided which controls the access to the message memory via the first buffer configuration, and at least one second finite state machine being provided which controls the access via the second buffer configuration, the at least one first finite state machine and the second finite state machine making access requests; and a third finite state machine being provided which assigns access to the message memory to the at least one first and the second finite state machine as a function of their access requests.

Claims

1-7. -7. (canceled)

8. A message handler of a communications module, comprising:

a message memory, in which data is input or output in response to an access;

a first buffer configuration;

a second buffer configuration, the message memory being connected to the first buffer configuration and the second buffer configuration, and the data being accessed via the first or the second buffer configuration;

at least one first finite state machine that controls the access to the message memory via the first buffer configuration;

at least one second finite state machine that controls the access via the second buffer configuration, the at least one first finite state machine and the second finite state machine making access requests; and

a third finite state machine that assigns access to the message memory to the at least one first finite state machine and the second finite state machine as a function of their access requests.

9. The message handler as recited in claim 8, wherein the data are transmitted via the first buffer configuration in two data paths having in each case two data directions, and the first buffer configuration contains a first buffer for a first data path and a second buffer for a second data path, and a first finite state machine is provided per data path, each of the two first finite state machines controlling the access to the message memory via one buffer each.

10. The message handler as recited in claim 8, further comprising:

a clock-pulse arrangement by which the data are transmitted in a specifiable clock-pulse period, and the third finite state machine assigns clock-pulse periods in succession to each first finite state machine and the second finite state machine as a function of their access requests.

11. The message handler as recited in claim 8, wherein depending on a number of simultaneous access requests, a total access time is distributed uniformly by the third finite state machine according to the number, only one access request ever being permissible simultaneously per finite state machine.

12. The message handler as recited in claim 8, wherein the message handler is arranged in a communications module.

13. A method for controlling access to data of a message memory of a communications module using a message handler, comprising:

inputting or outputting data into or out of the message memory in response to an access, the message memory being connected to a first buffer configuration and a second buffer configuration, and the data being accessed via the first or the second buffer configuration;

providing at least one first finite state machine that controls the access to the message memory via the first buffer configuration as a first access path; and

providing a second finite state machine that controls the access via the second buffer configuration as a second access path, the data being accessed on only one of the access paths at the same time.

14. The method as recited in claim 13, wherein the data are transmitted via the first buffer configuration in two data paths having in each case two data directions, and the first buffer configuration contains a first buffer for a first data path and a second buffer for a second data path, and one first finite state machine is provided per data path, each of the two first finite state machines controlling the access to the message memory via one buffer each, a third access path thereby resulting, and data being accessed on only one of the access paths at the same time here.