INTEGRATED MEMORY MANAGEMENT AND MEMORY MANAGEMENT METHOD

• US 20090083478A1
• Filed: 09/24/2008
• Published: 03/26/2009
• Est. Priority Date: 03/28/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sakamoto, Hiroyuki, Kunimatsu, Atsushi, Nakai, Hiroto, Maeda, Kenichi
• Granted Patent: US 8,135,900 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

Claims

1. An integrated memory management device comprising:

an acquiring unit acquiring a read destination logical address from a first processor of one or more processors;

an address conversion unit converting the read destination logical address acquired by the acquiring unit into a read destination physical address of a non-volatile main memory;

an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size of the non-volatile main memory or an integer multiple of the page size of the non-volatile main memory; and

a transmission unit transferring the read data to a cache memory of the first processor having a cache size that depends on the block size of the non-volatile main memory or the integer multiple of the page size of the non-volatile main memory.

2. A device according to claim 1,

wherein the acquiring unit acquires a write destination logical address and write data having the cache size from the first processor,

the address conversion unit converts the write destination logical address acquired by the acquiring unit into a write destination physical address of the non-volatile main memory, and

the access unit writes the write data in the non-volatile main memory at a position corresponding to the write destination physical address.

3. A device according to claim 2,

wherein the address conversion unit performs wear-leveling on the basis of at least one of read/write frequency information items peculiar to data, memory usage information including the number of read and write operations in each area of the non-volatile main memory, and memory peculiarity information including the page size and the block size of the non-volatile main memory, the number of times data can be rewritten in each memory area, and the number of times data can be read from each memory area.

4. A device according to claim 2,

wherein the non-volatile main memory is divided into areas having each group attribute, and comprises memory peculiarity information including the group attributes of the areas;

and

the address conversion unit accesses read/write frequency information items peculiar to data being defined by an operating of a file management program on the first processor and the memory peculiarity information, and decides the write destination physical address representing an area corresponding to the group attribute of the read/write frequency information items peculiar to data.

5. A device according to claim 1,

wherein the non-volatile main memory is a NAND type flash main memory.

6. A device according to claim 5, executing an operation of a memory controller of the NAND type flash main memory.

7. A device according to claim 1, executing an access for a virtual memory space being formed on the basis of the non-volatile main memory and cache memory.

8. A device according to claim 1, accessing for non-volatile main memories including the non-volatile main memory.

9. A device according to claim 8, executing a RAID operation for the non-volatile main memories,

wherein a swap target memory of the non-volatile main memories is able to swap when another memory of the non-volatile main memories is operating.

10. A memory management method comprising:

acquiring a read destination logical address from a first processor of one or more processors by an integrated memory management device;

converting the read destination logical address acquired into a read destination physical address of a non-volatile main memory by the integrated memory management device;

reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size of the non-volatile main memory or an integer multiple of the page size of the non-volatile main memory by the integrated memory management device; and

transferring the read data to a cache memory of the first processor having a cache size that depends on the block size of the non-volatile main memory or the integer multiple of the page size of the non-volatile main memory by the integrated memory management device.

11. A method according to claim 10, further comprising:

acquiring a write destination logical address and write data having the cache size from the first processor by the integrated memory management device;

converting the write destination logical address into a write destination physical address of the non-volatile main memory by the integrated memory management device; and

writing the write data in the non-volatile main memory at a position corresponding to the write destination physical address.

12. A method according to claim 11,

wherein the converting includes performing wear-leveling on the basis of at least one of read/write frequency information items peculiar to data, memory usage information including the number of read and write operations in each area of the non-volatile main memory, and memory peculiarity information including the page size and the block size of the non-volatile main memory, the number of times data can be rewritten in each memory area, and the number of times data can be read from each memory area.

13. A method according to claim 11,

wherein the non-volatile main memory is divided into areas having each group attribute, and comprises memory peculiarity information including the group attributes;

and

the converting includes accessing read/write frequency information items peculiar to data being defined by an operation of file management program on the first processor and the memory peculiarity information, and deciding the write destination physical address representing an area corresponding to the group attribute of the read/write frequency information items peculiar to data.

14. A method according to claim 10, wherein the non-volatile main memory is a NAND type flash main memory.

15. A method according to claim 14, wherein the integrated memory management device executes an operation of a memory controller of the NAND type flash main memory.

16. A method according to claim 10, wherein the integrated memory management device executes an access for a virtual memory space being formed on the basis of the non-volatile main memory and cache memory.

17. A method according to claim 10, wherein the integrated memory management device accesses for non-volatile main memories including the non-volatile main memory.

18. A method according to claim 17, wherein the integrated memory management device executes a RAID operation for the non-volatile main memories;

and

a swap target memory of the non-volatile main memories is able to swap when another memory of the non-volatile main memories is operating.